From patchwork Fri Feb 16 14:18:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13560084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0977BC48260 for ; Fri, 16 Feb 2024 14:25:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F87B10E26B; Fri, 16 Feb 2024 14:25:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dhUVL47B"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id ADBEA10E074; Fri, 16 Feb 2024 14:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708093526; x=1739629526; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=t+Tl46SHSVfbWWXJ5i6E6dq3KpzKRJy+BlzikHqP4qM=; b=dhUVL47BzGepupMwf31HG4ojoYQEUe2XYt9PL8OLRpNe3R2bfcG87sIH 6oPsB2LK0qrE0lxkYy8HIdz0ZFGvFG2UyeXKNbym0KQ8LA44xTKsfYNVS Fiy482W7EkOvqdwqum9aIcXlZHyYeiw1tLVuBbFPiRqM31D9k2YH+c8cT qvC0DYFErE2eUVUPDsBBruQiuAkDo9pc5Gd+zdyuUSjKeAutrnoIsI7+W lvpM55wVrkVwHGS1eESrfRUALthbBT/QezUhTeCJePgTvlxU0CPUMUXwZ o9b4t0P1C5lHlMkirc7rila5WzHkAzeK6l5myNQ/Ui7yv3psfzezY7rFj w==; X-IronPort-AV: E=McAfee;i="6600,9927,10985"; a="2372043" X-IronPort-AV: E=Sophos;i="6.06,164,1705392000"; d="scan'208";a="2372043" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2024 06:25:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,164,1705392000"; d="scan'208";a="34639120" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa002.jf.intel.com with ESMTP; 16 Feb 2024 06:25:23 -0800 From: Mitul Golani To: intel-gfx-trybot@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, dri-devel@lists.freedesktop.org, Mitul Golani Subject: [PATCH 0/6] Enable Adaptive Sync SDP Support for DP Date: Fri, 16 Feb 2024 19:48:22 +0530 Message-Id: <20240216141828.1884193-1-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" An Adaptive Sync SDP allows a DP protocol converter to forward Adaptive Sync video with minimal buffering overhead within the converter. An Adaptive-Sync-capable DP protocol converter indicates its support by setting the related bit in the DPCD register. Computes AS SDP values based on the display configuration, ensuring proper handling of Variable Refresh Rate (VRR) in the context of Adaptive Sync. --v2: - Update logging to Patch-1 - use as_sdp instead of async - Put definitions to correct placeholders from where it is defined. - Update member types of as_sdp for uniformity. - Correct use of REG_BIT and REG_GENMASK. - Remove unrelated comments and changes. - Correct code indents. - separate out patch changes for intel_read/write_dp_sdp. --v3: - Add VIDEO_DIP_ASYNC_DATA_SIZE definition and comment in as_sdp_pack function to patch 2 as originally used there. [Patch 2]. - Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes [Patch 3]. --v4: - Add check for HAS_VRR before writing AS SDP. [Patch 3]. --v5: - Add missing check for HAS_VRR before reading AS SDP as well [Patch 3]. --v6: - Rebase all patches. - Compute TRANS_VRR_VSYNC. -v7: - Move vrr_vsync_start/end to compute config. - Use correct function for drm_debug_printer. -v8: - Code refactoring. - Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit) - Update bit fields of VRR_VSYNC_START/END.(Ankit) - Send patches to dri-devel.(Ankit) - Update definition names for AS SDP which are starting from HSW, as these defines are applicable for ADLP+.(Ankit) - Remove unused bitfield define, AS_SDP_ENABLE. - Add support in drm for Adaptive Sync sink status, which can be used later as a check for read/write sdp. (Ankit) Mitul Golani (6): drm/dp: Add an support to indicate if sink supports AS SDP drm: Add Adaptive Sync SDP logging drm/i915/dp: Add Read/Write support for Adaptive Sync SDP drm/i915/display: Compute and Enable AS SDP drm/i915/display: Compute vrr_vsync params drm/i915/display: Read/Write AS sdp only when sink/source has enabled drivers/gpu/drm/display/drm_dp_helper.c | 37 +++++ .../drm/i915/display/intel_crtc_state_dump.c | 12 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 4 + .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 130 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 12 +- drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++ drivers/gpu/drm/i915/i915_reg.h | 19 +++ include/drm/display/drm_dp.h | 2 + include/drm/display/drm_dp_helper.h | 34 +++++ 12 files changed, 264 insertions(+), 4 deletions(-)