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Mon, 03 Mar 2025 07:14:46 -0800 (PST) Received: from [127.0.1.1] ([112.64.60.252]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736584b3cffsm1851984b3a.4.2025.03.03.07.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 07:14:46 -0800 (PST) From: Jun Nie Subject: [PATCH v8 00/15] drm/msm/dpu: Support quad pipe with dual-DSI Date: Mon, 03 Mar 2025 23:14:29 +0800 Message-Id: <20250303-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v8-0-eb5df105c807@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAFXHxWcC/63OQQ7CIBAF0KsY1o6h0EJ15T2MCyyDJdqCQ62ap neXutK9y/+TmfcnlpA8JrZbTYxw9MmHPod6vWJNa/ozgrc5M8FFxUWhIXW1qjiMCooS2s6CxeZ iyEJnU4Lb3Vi4xzQQmg7C1Z5CGB5kYkQCqSASRkDJt27raimVYRnKpfPPz4jDMefWpyHQ67NpV Ev7Vz7fcmiKosw/dSmV3l99byhsAp3Z4o/6yxTqL6bOZm0rV7lSKDyJH3Oe5zfxekogiQEAAA= = X-Change-ID: 20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-e309f9f8336a To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741014878; l=5837; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=1G9+v+xHSV6e/Cc3fWuThPAWhwSF7iYoH/iluRyVxpM=; b=lnFFMORGnWu/x1BqCoAxxyw9PYcRBIteWY9/UwYrdm15EPnAs32HoqEaAGPbgIWvY5DC7goGp iSCzZ6IDgdPA4y6RSiw9Y9Pd+TyyKCD2x8+/X/JnUp7zYJsxvYxy8pZ X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 2 or more SSPPs and dual-DSI interface are need for super wide panel. And 4 DSC are preferred for power optimal in this case due to width limitation of SSPP and MDP clock rate constrain. This patch set extends number of pipes to 4 and revise related mixer blending logic to support quad pipe. All these changes depends on the virtual plane feature to split a super wide drm plane horizontally into 2 or more sub clip. Thus DMA of multiple SSPPs can share the effort of fetching the whole drm plane. The first pipe pair co-work with the first mixer pair to cover the left half of screen and 2nd pair of pipes and mixers are for the right half of screen. If a plane is only for the right half of screen, only one or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is assinged for invalid pipe. For those panel that does not require quad-pipe, only 1 or 2 pipes in the 1st pipe pair will be used. There is no concept of right half of screen. For legacy non virtual plane mode, the first 1 or 2 pipes are used for the single SSPP and its multi-rect mode. To test bonded DSI on SM8650, the 5 patches for active-CTL improvement are needed: https://gitlab.freedesktop.org/lumag/msm/-/commits/dpu-4k?ref_type=heads Changes in v8: - Fix looping pipes of a plane in _dpu_plane_color_fill() - Improve pipe assignment with deleting pipes loop in stage. - Define PIPES_PER_PLANE properly when it appears fisrt. - rename lms_in_pair to lms_in_stage to avoid confusion. - Add review tags. - Link to v7: https://lore.kernel.org/r/20250226-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v7-0-8d5f5f426eb2@linaro.org Changes in v7: - Improve pipe assignment to avoid point to invalid memory. - Define STAGES_PER_PLANE as 2 only when quad-pipe is introduced. - Polish LM number when blending pipes with min() and pull up to caller func. - Add review tags. - Link to v6: https://lore.kernel.org/r/20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v6-0-c11402574367@linaro.org Changes in v6: - Replace LM number with PP number to calculate PP number per encoder. - Rebase to Linux v6.14-rc2. - Add review tags. - Link to v5: https://lore.kernel.org/r/20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org Changes in v5: - Iterate SSPP flushing within the required mixer pair, instead of all active mixers or specific mixer. - Limit qaud-pipe usage case to SoC with 4 or more DSC engines and 2 interfaces case. - Remove valid flag and use width for pipe validation. - Polish commit messages and code comments. - Link to v4: https://lore.kernel.org/r/20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org Changes in v4: - Restrict SSPP flushing to the required mixer, instead of all active mixers. - Polish commit messages and code comments. - Rebase to latest msm/drm-next branch. - Move pipe checking patch to the top of patch set. - Link to v3: https://lore.kernel.org/dri-devel/20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org Changes in v3: - Split change in trace into a separate patch. - Rebase to latest msm-next branch. - Reorder patch sequence to make sure valid flag is set in earlier patch - Rectify rewrite patch to move logic change into other patch - Polish commit messages and code comments. - Link to v2: https://lore.kernel.org/dri-devel/20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org Changes in v2: - Revise the patch sequence with changing to 2 pipes topology first. Then prepare for quad-pipe setup, then enable quad-pipe at last. - Split DSI patches into other patch set. - Link to v1: https://lore.kernel.org/all/20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5a2e@linaro.org Signed-off-by: Jun Nie --- Jun Nie (15): drm/msm/dpu: check every pipe per capability drm/msm/dpu: Do not fix number of DSC drm/msm/dpu: configure DSC per number in use drm/msm/dpu: polish log for resource allocation drm/msm/dpu: decide right side per last bit drm/msm/dpu: fix mixer number counter on allocation drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation drm/msm/dpu: bind correct pingpong for quad pipe drm/msm/dpu: Add pipe as trace argument drm/msm/dpu: handle pipes as array drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer drm/msm/dpu: blend pipes per mixer pairs config drm/msm/dpu: support SSPP assignment for quad-pipe case drm/msm/dpu: support plane splitting in quad-pipe case drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 89 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 70 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 404 ++++++++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 215 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 32 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- 12 files changed, 516 insertions(+), 342 deletions(-) --- base-commit: b44251a8c179381b9f3ed3aa49be04fe1d516903 change-id: 20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-e309f9f8336a Best regards,