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[v3,0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms

Message ID 20250307-dpu-active-ctl-v3-0-5d20655f10ca@linaro.org (mailing list archive)
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Series drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms | expand

Message

Dmitry Baryshkov March 7, 2025, 6:24 a.m. UTC 
Since version 5.0 the DPU got an improved way of handling multi-output
configurations. It is now possible to program all pending changes
through a single CTL and flush everything at the same time.

Implement corresponding changes in the DPU driver.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in v3:
- Rebased on top of msm-next
- Link to v2: https://lore.kernel.org/r/20250228-dpu-active-ctl-v2-0-9a9df2ee5193@linaro.org

Changes in v2:
- Made CTL_MERGE_3D_ACTIVE writes unconditional (Marijn)
- Added CTL_INTF_MASTER clearing in dpu_hw_ctl_reset_intf_cfg_v1
  (Marijn)
- Added a patch to drop extra rm->has_legacy_ctls condition (and an
  explanation why it can not be folded in an earlier patch).
- Link to v1: https://lore.kernel.org/r/20250220-dpu-active-ctl-v1-0-71ca67a564f8@linaro.org

---
Dmitry Baryshkov (8):
      drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE register
      drm/msm/dpu: program master INTF value
      drm/msm/dpu: pass master interface to CTL configuration
      drm/msm/dpu: use single CTL if it is the only CTL returned by RM
      drm/msm/dpu: don't select single flush for active CTL blocks
      drm/msm/dpu: allocate single CTL for DPU >= 5.0
      drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0
      drm/msm/dpu: drop now-unused condition for has_legacy_ctls

 .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h    |  5 ++---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h |  5 ++---
 .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h    |  4 ++--
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h |  4 ++--
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h |  5 ++---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h |  5 ++---
 .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h   |  5 ++---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h |  5 ++---
 .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h    |  5 ++---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h |  5 ++---
 .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h   |  5 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  6 +++++-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  2 ++
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  5 ++++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         | 20 ++++++++++++++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h         |  2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 25 +++++++++++-----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |  2 ++
 18 files changed, 67 insertions(+), 48 deletions(-)
---
base-commit: 565351ae7e0cee80e9b5ed84452a5b13644ffc4d
change-id: 20250209-dpu-active-ctl-08cca4d8b08a

Best regards,