@@ -16,6 +16,7 @@ Required properties:
+ "arm,mali-t880"
* which must be preceded by one of the following vendor specifics:
+ "amlogic,meson-gxm-mali"
+ + "arm,juno-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
@@ -35,6 +35,18 @@
clock-names = "apb_pclk";
};
+ smmu_gpu: iommu@2b400000 {
+ compatible = "arm,mmu-400", "arm,smmu-v1";
+ reg = <0x0 0x2b400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ power-domains = <&scpi_devpd 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
smmu_pcie: iommu@2b500000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x2b500000 0x0 0x10000>;
@@ -487,6 +499,19 @@
};
};
+ gpu: gpu@2d000000 {
+ compatible = "arm,juno-mali", "arm,mali-t624";
+ reg = <0 0x2d000000 0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpu", "job", "mmu";
+ clocks = <&scpi_dvfs 2>;
+ power-domains = <&scpi_devpd 3>;
+ dma-coherent;
+ status = "disabled";
+ };
+
sram: sram@2e000000 {
compatible = "arm,juno-sram-ns", "mmio-sram";
reg = <0x0 0x2e000000 0x0 0x8000>;
Since we now have bindings for Mali Midgard GPUs, let's use them to describe Juno's GPU subsystem, if only because we can. Juno sports a Mali-T624 integrated behind an MMU-400 (as a gesture towards virtualisation), in their own dedicated power domain with DVFS controlled by the SCP. Signed-off-by: Robin Murphy <robin.murphy@arm.com> --- Just in case anyone else is interested. Note that I've not been using this exact patch, since my Juno is running the new SCMI-based firmware which needs not-yet-upstream MHU changes, but this should in theory be the equivalent change for the upstream SCPI-based DT. .../bindings/gpu/arm,mali-midgard.txt | 1 + arch/arm64/boot/dts/arm/juno-base.dtsi | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+)