From patchwork Fri Nov 13 17:21:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Ser X-Patchwork-Id: 11904347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 713FAC388F7 for ; Fri, 13 Nov 2020 17:21:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5F68421D1A for ; Fri, 13 Nov 2020 17:21:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5F68421D1A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=emersion.fr Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FA2E6E5A0; Fri, 13 Nov 2020 17:21:44 +0000 (UTC) Received: from mail-40133.protonmail.ch (mail-40133.protonmail.ch [185.70.40.133]) by gabe.freedesktop.org (Postfix) with ESMTPS id 487DD6E59B for ; Fri, 13 Nov 2020 17:21:43 +0000 (UTC) Date: Fri, 13 Nov 2020 17:21:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=emersion.fr; s=protonmail2; t=1605288100; bh=D60csVvyZkJMwUAF2Xl2ltkvMiW0+tALBjS2O0sVEqA=; h=Date:To:From:Cc:Reply-To:Subject:From; b=VI9SmC8dplLBuKXo9E3i50An0di5CDiBPc1IKtZy0A9hW0FXK1v+cVUoHFX6Zce9E o41fX9OyCGiM3TtXbUy2udhYrjJ+EKqwRz7PDKnGg4HnXiERoBpceshKftSLhc0TTG 9pNKlb7PU5NPO9dUXdpqF+hUK5wm7XDsElYjTo6f7N34l7kAqO0fbRN2D1txA1iiuf BiWvbiQVhlt89zRcab2+Q/1bNgemzUDwk5uORZt6nIS1FtnPMJuVJYUNtiDbuHLKYb vNbIorY+0RZoTG/Ubz0tnckIUM3Y51ke1IHEdSUriQjG5WXvTc14gr5jKWS1wx8V3T ktao3+b8GeyIA== To: amd-gfx@lists.freedesktop.org From: Simon Ser Subject: [PATCH] drm/fourcc: add table describing AMD modifiers bit layout Message-ID: <0gLrKmUEE4VjN5rdf6dUiejliU1GhjCBvH7RFMQYY@cp7-web-044.plabs.ch> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Simon Ser Cc: dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The table describes how each bit in the u64 value is used. Explicitly state which values a field can take if we have defines for them. Also add a note when a field isn't always populated. Forcing people to update the table when changing the bit layout should make it more obvious when there's a mistake, I hope. If we get to the point where the bit layout gets more complicated, it might be worth it to split the table into multiple tables (e.g. one for GFX8, one for GFX9+, and so on). Signed-off-by: Simon Ser Cc: Bas Nieuwenhuizen Cc: Alex Deucher Cc: Daniel Vetter --- This already contains the fix in [1]. [1]: https://lists.freedesktop.org/archives/amd-gfx/2020-November/056073.html include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index ca48ed0e6bc1..253386b7bc6a 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -1114,6 +1114,25 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * * For multi-plane formats the above surfaces get merged into one plane for * each format plane, based on the required alignment only. + * + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* + * 13 DCC + * 14 DCC_RETILE + * 15 DCC_PIPE_ALIGN + * 16 DCC_INDEPENDENT_64B + * 17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + * 20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITS Only for some chips + * 26:24 BANK_XOR_BITS Only for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 - Reserved for future use, must be zero */ #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)