From patchwork Sat Feb 20 23:15:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 80985 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1KNGQ0X022232 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sat, 20 Feb 2010 23:17:02 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NiyXg-0005Ih-69; Sat, 20 Feb 2010 23:15:20 +0000 Received: from sfi-mx-1.v28.ch3.sourceforge.com ([172.29.28.121] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NiyXf-0005Ib-7h for dri-devel@lists.sourceforge.net; Sat, 20 Feb 2010 23:15:19 +0000 Received-SPF: pass (sfi-mx-1.v28.ch3.sourceforge.com: domain of gmail.com designates 209.85.220.214 as permitted sender) client-ip=209.85.220.214; envelope-from=zajec5@gmail.com; helo=mail-fx0-f214.google.com; Received: from mail-fx0-f214.google.com ([209.85.220.214]) by sfi-mx-1.v28.ch3.sourceforge.com with esmtp (Exim 4.69) id 1NiyXc-0002ee-PJ for dri-devel@lists.sourceforge.net; Sat, 20 Feb 2010 23:15:19 +0000 Received: by fxm6 with SMTP id 6so1282841fxm.2 for ; Sat, 20 Feb 2010 15:15:10 -0800 (PST) Received: by 10.87.55.5 with SMTP id h5mr19730105fgk.4.1266707710090; Sat, 20 Feb 2010 15:15:10 -0800 (PST) Received: from localhost.localdomain (77-253-200-80.ip.netia.com.pl [77.253.200.80]) by mx.google.com with ESMTPS id 16sm739434fxm.7.2010.02.20.15.15.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 20 Feb 2010 15:15:09 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: dri-devel@lists.sourceforge.net, Dave Airlie Subject: [PATCH V2] drm/radeon/kms: simplify storing current and requested PM mode Date: Sun, 21 Feb 2010 00:15:04 +0100 Message-Id: <1266707704-2990-1-git-send-email-zajec5@gmail.com> X-Mailer: git-send-email 1.6.4.2 MIME-Version: 1.0 X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record -0.0 DKIM_VERIFIED Domain Keys Identified Mail: signature passes verification 0.0 DKIM_SIGNED Domain Keys Identified Mail: message has a signature X-Headers-End: 1NiyXc-0002ee-PJ X-BeenThere: dri-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 20 Feb 2010 23:17:03 +0000 (UTC) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 0ca83ca..fc9044e 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -652,9 +652,6 @@ struct radeon_power_state { struct radeon_pm_clock_info clock_info[8]; /* number of valid clock modes in this power state */ int num_clock_modes; - /* currently selected clock mode */ - struct radeon_pm_clock_info *current_clock_mode; - struct radeon_pm_clock_info *requested_clock_mode; struct radeon_pm_clock_info *default_clock_mode; /* non clock info about this state */ struct radeon_pm_non_clock_info non_clock_info; @@ -691,7 +688,9 @@ struct radeon_pm { /* number of valid power states */ int num_power_states; struct radeon_power_state *current_power_state; + struct radeon_pm_clock_info *current_clock_mode; struct radeon_power_state *requested_power_state; + struct radeon_pm_clock_info *requested_clock_mode; struct radeon_power_state *default_power_state; }; diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 79d4453..33aed6c 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1450,7 +1450,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); rdev->pm.default_power_state = NULL; - rdev->pm.current_power_state = NULL; if (power_info) { if (frev < 4) { @@ -1517,11 +1516,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; } state_index++; break; @@ -1586,11 +1582,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; } state_index++; break; @@ -1661,11 +1654,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; } state_index++; break; @@ -1765,11 +1755,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].type = POWER_STATE_TYPE_DEFAULT; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; } state_index++; } @@ -1788,18 +1775,19 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev) rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = - &rdev->pm.power_state[state_index].clock_info[0]; rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; if (rdev->asic->get_pcie_lanes) rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); else rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; state_index++; } rdev->pm.num_power_states = state_index; + + rdev->pm.current_power_state = rdev->pm.default_power_state; + rdev->pm.current_clock_mode = + rdev->pm.default_power_state->default_clock_mode; } void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 5ef791b..69af81d 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -2358,7 +2358,6 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev) int state_index = 0; rdev->pm.default_power_state = NULL; - rdev->pm.current_power_state = NULL; if (rdev->flags & RADEON_IS_MOBILITY) { offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); @@ -2447,15 +2446,17 @@ default_mode: rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; - rdev->pm.power_state[state_index].current_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; if (rdev->asic->get_pcie_lanes) rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); else rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; - rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; rdev->pm.num_power_states = state_index + 1; + + rdev->pm.current_power_state = rdev->pm.default_power_state; + rdev->pm.current_clock_mode = + rdev->pm.default_power_state->default_clock_mode; } void radeon_external_tmds_setup(struct drm_encoder *encoder) diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 6dbfdf4..8960acf 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -143,50 +143,50 @@ static void radeon_get_power_state(struct radeon_device *rdev, enum radeon_pm_action action) { switch (action) { - case PM_ACTION_NONE: - default: - rdev->pm.requested_power_state = rdev->pm.current_power_state; - rdev->pm.requested_power_state->requested_clock_mode = - rdev->pm.requested_power_state->current_clock_mode; - break; case PM_ACTION_MINIMUM: rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY); - rdev->pm.requested_power_state->requested_clock_mode = + rdev->pm.requested_clock_mode = radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW); break; case PM_ACTION_DOWNCLOCK: rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE); - rdev->pm.requested_power_state->requested_clock_mode = + rdev->pm.requested_clock_mode = radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID); break; case PM_ACTION_UPCLOCK: rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT); - rdev->pm.requested_power_state->requested_clock_mode = + rdev->pm.requested_clock_mode = radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH); break; + case PM_ACTION_NONE: + default: + DRM_ERROR("Requested mode for not defined action\n"); + return; } DRM_INFO("Requested: e: %d m: %d p: %d\n", - rdev->pm.requested_power_state->requested_clock_mode->sclk, - rdev->pm.requested_power_state->requested_clock_mode->mclk, + rdev->pm.requested_clock_mode->sclk, + rdev->pm.requested_clock_mode->mclk, rdev->pm.requested_power_state->non_clock_info.pcie_lanes); } static void radeon_set_power_state(struct radeon_device *rdev) { - if (rdev->pm.requested_power_state == rdev->pm.current_power_state) + /* if *_clock_mode are the same, *_power_state are as well */ + if (rdev->pm.requested_clock_mode == rdev->pm.current_clock_mode) return; DRM_INFO("Setting: e: %d m: %d p: %d\n", - rdev->pm.requested_power_state->requested_clock_mode->sclk, - rdev->pm.requested_power_state->requested_clock_mode->mclk, + rdev->pm.requested_clock_mode->sclk, + rdev->pm.requested_clock_mode->mclk, rdev->pm.requested_power_state->non_clock_info.pcie_lanes); /* set pcie lanes */ /* set voltage */ /* set engine clock */ - radeon_set_engine_clock(rdev, rdev->pm.requested_power_state->requested_clock_mode->sclk); + radeon_set_engine_clock(rdev, rdev->pm.requested_clock_mode->sclk); /* set memory clock */ rdev->pm.current_power_state = rdev->pm.requested_power_state; + rdev->pm.current_clock_mode = rdev->pm.requested_clock_mode; } int radeon_pm_init(struct radeon_device *rdev)