From patchwork Thu Mar 11 21:19:16 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 85101 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2BLt1IJ021069 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 11 Mar 2010 21:55:38 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-1.v29.ch3.sourceforge.com) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NpqKZ-0003ao-Cs; Thu, 11 Mar 2010 21:54:11 +0000 Received: from sfi-mx-3.v28.ch3.sourceforge.com ([172.29.28.123] helo=mx.sourceforge.net) by sfs-ml-2.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NppvM-0005ha-Kp for dri-devel@lists.sourceforge.net; Thu, 11 Mar 2010 21:28:08 +0000 X-ACL-Warn: Received: from cable-static-49-187.intergga.ch ([157.161.49.187] helo=mail.ffwll.ch) by sfi-mx-3.v28.ch3.sourceforge.com with esmtp (Exim 4.69) id 1NppvK-0003DM-9u for dri-devel@lists.sourceforge.net; Thu, 11 Mar 2010 21:28:08 +0000 Received: by mail.ffwll.ch (Postfix, from userid 1000) id 83F0620C221; Thu, 11 Mar 2010 22:19:37 +0100 (CET) X-Spam-ASN: X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on orange.ffwll.ch X-Spam-Level: X-Spam-Hammy: 0.000-+--HTo:D*sourceforge.net, 0.000-+--HTo:D*lists.sourceforge.net, 0.000-+--struct X-Spam-Status: No, score=-4.4 required=6.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.2.5 X-Spam-Spammy: 0.956-+--H*m:ffwll, 0.956-+--H*r:mail.ffwll.ch, 0.953-+--H*Ad:U*daniel.vetter Received: from viiv.ffwll.ch (viiv.ffwll.ch [192.168.23.128]) by mail.ffwll.ch (Postfix) with ESMTP id 9FC4320C208; Thu, 11 Mar 2010 22:19:21 +0100 (CET) Received: from daniel by viiv.ffwll.ch with local (Exim 4.71) (envelope-from ) id 1Nppmr-000286-7h; Thu, 11 Mar 2010 22:19:21 +0100 From: Daniel Vetter To: dri-devel@lists.sourceforge.net Subject: [PATCH 3/5] drm/radeon: unconfuse return value of radeon_asic->clear_surface_reg Date: Thu, 11 Mar 2010 22:19:16 +0100 Message-Id: <1268342358-7532-4-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1268342358-7532-1-git-send-email-daniel.vetter@ffwll.ch> References: <1268342358-7532-1-git-send-email-daniel.vetter@ffwll.ch> X-Spam-Score: 0.0 (/) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. _SUMMARY_ X-Headers-End: 1NppvK-0003DM-9u X-Mailman-Approved-At: Thu, 11 Mar 2010 21:54:09 +0000 Cc: Daniel Vetter X-BeenThere: dri-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 11 Mar 2010 21:55:38 +0000 (UTC) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 63cc609..c51ae43 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -782,7 +782,7 @@ struct radeon_asic { int (*set_surface_reg)(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size); - int (*clear_surface_reg)(struct radeon_device *rdev, int reg); + void (*clear_surface_reg)(struct radeon_device *rdev, int reg); void (*bandwidth_update)(struct radeon_device *rdev); void (*hpd_init)(struct radeon_device *rdev); void (*hpd_fini)(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 2bc2623..4c0d3da 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -73,7 +73,7 @@ int r100_copy_blit(struct radeon_device *rdev, int r100_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size); -int r100_clear_surface_reg(struct radeon_device *rdev, int reg); +void r100_clear_surface_reg(struct radeon_device *rdev, int reg); void r100_bandwidth_update(struct radeon_device *rdev); void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); int r100_ring_test(struct radeon_device *rdev); @@ -212,7 +212,7 @@ int r600_gpu_reset(struct radeon_device *rdev); int r600_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size); -int r600_clear_surface_reg(struct radeon_device *rdev, int reg); +void r600_clear_surface_reg(struct radeon_device *rdev, int reg); void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); int r600_ring_test(struct radeon_device *rdev); int r600_copy_blit(struct radeon_device *rdev,