From patchwork Thu Sep 30 23:16:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 221522 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o8UNGVM9029390 for ; Thu, 30 Sep 2010 23:16:52 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 175109EB4B for ; Thu, 30 Sep 2010 16:16:30 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qy0-f176.google.com (mail-qy0-f176.google.com [209.85.216.176]) by gabe.freedesktop.org (Postfix) with ESMTP id B13A89E7A1 for ; Thu, 30 Sep 2010 16:16:20 -0700 (PDT) Received: by qyk36 with SMTP id 36so3176790qyk.14 for ; Thu, 30 Sep 2010 16:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=ZKkK9u6E7EHhcnTYXMW7qtzFwwv7j/+noQk5QW4CNVA=; b=riR1WxMVRo4w+nZ3QadJQx8Ab6TlAgSv2gCThrpO/DmBCxPutCf3Mi5TvqWG6wNCIt 9nR6N40X53unSshJooDY4mLRYH2KB9ebBhW9GczG2Fhmk5SN5bj5sSVdQnZHNgsr3pxA iL9rBl5/LcGyPOuaNu65c/uePet8BPs4Puq+w= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=QaIgskpQwAv/OkdOp5kel2J2jl6Eo+b0OaQr8aMoY3g5evo+kwCMMBitigG1fFQd07 0jRBFRjRgQ+DbUmk/skZvvNCmiM5EoeMYOYvM5VwTeB4cA2B29e6JOskrQ0m3jg8oKuk jH0XpPwr/pUpENazYOtl4R67gi6mdbg5bwJPs= Received: by 10.224.3.3 with SMTP id 3mr3190373qal.32.1285888576450; Thu, 30 Sep 2010 16:16:16 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-7.washdc.fios.verizon.net [74.96.105.7]) by mx.google.com with ESMTPS id t24sm448175qcs.47.2010.09.30.16.16.14 (version=SSLv3 cipher=RC4-MD5); Thu, 30 Sep 2010 16:16:15 -0700 (PDT) From: Alex Deucher To: airlied@gmail.com, dri-devel@lists.freedesktop.org Subject: [PATCH] drm/radeon/kms: properly handle 40 bit MC addresses in the cursor code Date: Thu, 30 Sep 2010 19:16:03 -0400 Message-Id: <1285888563-3560-1-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.1.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 30 Sep 2010 23:16:52 +0000 (UTC) diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index 5731fc9..4a81025 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c @@ -118,22 +118,25 @@ static void radeon_show_cursor(struct drm_crtc *crtc) } static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, - uint32_t gpu_addr) + uint64_t gpu_addr) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct radeon_device *rdev = crtc->dev->dev_private; if (ASIC_IS_DCE4(rdev)) { - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); + WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, + upper_32_bits(gpu_addr)); + WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, + gpu_addr & 0xffffffff); } else if (ASIC_IS_AVIVO(rdev)) { if (rdev->family >= CHIP_RV770) { if (radeon_crtc->crtc_id) - WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); + WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); else - WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); + WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); } - WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); + WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, + gpu_addr & 0xffffffff); } else { radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; /* offset is from DISP(2)_BASE_ADDRESS */