From patchwork Tue Apr 26 17:27:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 733382 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3QHW63F024279 for ; Tue, 26 Apr 2011 17:32:27 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F7EA9E943 for ; Tue, 26 Apr 2011 10:32:06 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qw0-f49.google.com (mail-qw0-f49.google.com [209.85.216.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A5FB9EAFD for ; Tue, 26 Apr 2011 10:27:53 -0700 (PDT) Received: by qwi2 with SMTP id 2so451734qwi.36 for ; Tue, 26 Apr 2011 10:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer; bh=ud11Zg/cv+tmmbhMvU+wnFk+YlfGAYIf3UpTGtcwxSA=; b=rmA8S24XvZ/LJlJObxMZF5rqjLpPHlAozX/VLYziOJwBehOvKPZJDp4DzMWYpgFFGO T+vLrTk3OVBB2DF4MTTfb38kv3ttSzr/0iqbKpmRXkwvfRTP8SqZay642E7OiMLKPnIw gHNC00gM0anDlJxRxZfWhYEM4KbG/n93GlXO4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=JaL2W6CF67oEtaS9bTdD1pLVeRHh1a4l/EqqSszgUS5hA2IfgNHjcBfZPrOOnksXGq rzs3xWY0SX9uZzw09fkHFHTABSZG82rKRpksc2qMI/0BibVgkHrZ6GAWfN8krSbQdjtu Ted1mSJLCBlu8Ci1OrucNDL2n2/2HdpCpQ5Xo= Received: by 10.224.186.9 with SMTP id cq9mr858807qab.246.1303838872513; Tue, 26 Apr 2011 10:27:52 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-7.washdc.fios.verizon.net [74.96.105.7]) by mx.google.com with ESMTPS id l38sm3959528qck.18.2011.04.26.10.27.51 (version=SSLv3 cipher=OTHER); Tue, 26 Apr 2011 10:27:51 -0700 (PDT) From: Alex Deucher To: airlied@gmail.com, dri-devel@lists.freedesktop.org Subject: [PATCH] drm/radeon/kms: add info query for tile pipes Date: Tue, 26 Apr 2011 13:27:43 -0400 Message-Id: <1303838863-24768-1-git-send-email-alexdeucher@gmail.com> X-Mailer: git-send-email 1.7.1.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 26 Apr 2011 17:32:27 +0000 (UTC) needed by mesa for htile setup. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_kms.c | 13 +++++++++++++ include/drm/radeon_drm.h | 1 + 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index bf7d4c0..871df03 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -221,6 +221,19 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; } break; + case RADEON_INFO_NUM_TILE_PIPES: + if (rdev->family >= CHIP_CAYMAN) + value = rdev->config.cayman.max_tile_pipes; + else if (rdev->family >= CHIP_CEDAR) + value = rdev->config.evergreen.max_tile_pipes; + else if (rdev->family >= CHIP_RV770) + value = rdev->config.rv770.max_tile_pipes; + else if (rdev->family >= CHIP_R600) + value = rdev->config.r600.max_tile_pipes; + else { + return -EINVAL; + } + break; default: DRM_DEBUG_KMS("Invalid request %d\n", info->request); return -EINVAL; diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index 3bce1a4..7aa5ddd 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h @@ -909,6 +909,7 @@ struct drm_radeon_cs { #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ #define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ +#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ struct drm_radeon_info { uint32_t request;