From patchwork Sun Jul 29 17:04:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TWFyZWsgT2zFocOhaw==?= X-Patchwork-Id: 1252511 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id BF8FB3FCFC for ; Sun, 29 Jul 2012 17:05:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 91AB39EFE2 for ; Sun, 29 Jul 2012 10:05:07 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id B4CC09E7E1 for ; Sun, 29 Jul 2012 10:04:51 -0700 (PDT) Received: by wgbdr1 with SMTP id dr1so3429552wgb.12 for ; Sun, 29 Jul 2012 10:04:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references; bh=8b2EHmfUzZDFw1tzyPBz71qiUQAYx4Ru3fVDV+gCp6I=; b=Tgoidn3D03q36Ec5ncnYCq4YiAQhlyL1SMYsM8ecAdM2OvRFp1rPS9p1BbI6OUYuaC HTjZ2rW0Ks6O1xmTsi8Qdy1RzJPbAhoofQ2ZnJaRpXmzR6/YEQxOILYMiC6uIeEwCON6 l2Ex7ahU3IsWHHguhHkNR13pQvXoxX4dj+zC+e/8rTnWQHPERVXDmfxFntXLS2TAkSSz 8082RKRqRfvah5Puun5sU0UtQNX8q04dIn2yR80WFURD/YYx3/wDu8WzvYw/NVnvkqN9 CRfKUR0oWehIqf+9nD15OwcraUhxJkVpsRCM2C2ear7kcoEBZ1JuiXszlbO3VNqdo5Xt rZIQ== Received: by 10.180.87.199 with SMTP id ba7mr36350941wib.10.1343581490713; Sun, 29 Jul 2012 10:04:50 -0700 (PDT) Received: from localhost.localdomain (static-84-242-70-218.net.upcbroadband.cz. [84.242.70.218]) by mx.google.com with ESMTPS id w7sm11636490wiz.0.2012.07.29.10.04.49 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 29 Jul 2012 10:04:49 -0700 (PDT) From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG Date: Sun, 29 Jul 2012 19:04:27 +0200 Message-Id: <1343581467-27881-1-git-send-email-maraeo@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343570522-4080-2-git-send-email-maraeo@gmail.com> References: <1343570522-4080-2-git-send-email-maraeo@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org If we don't need stencil, don't allocate it. If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth. v2: actually do it correctly --- radeon/radeon_surface.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 5800c33..874a092 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -604,7 +604,11 @@ static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, } } - if (surf->flags & RADEON_SURF_SBUFFER) { + /* The depth and stencil buffers are in separate resources on evergreen. + * We allocate them in one buffer next to each other to simplify + * communication between the DDX and the Mesa driver. */ + if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == + (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); surf->bo_size = surf->stencil_offset + surf->bo_size / 4; } @@ -656,7 +660,8 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, } } - if (surf->flags & RADEON_SURF_SBUFFER) { + if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) == + (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); surf->bo_size = surf->stencil_offset + surf->bo_size / 4; } @@ -752,14 +757,7 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; - /* for some reason eg need to have room for stencil right after depth */ - if (surf->flags & RADEON_SURF_ZBUFFER) { - surf->flags |= RADEON_SURF_SBUFFER; - } - if (surf->flags & RADEON_SURF_SBUFFER) { - surf->flags |= RADEON_SURF_ZBUFFER; - } - if (surf->flags & RADEON_SURF_ZBUFFER) { + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { /* zbuffer only support 1D or 2D tiled surface */ switch (mode) { case RADEON_SURF_MODE_1D: @@ -828,11 +826,6 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; - /* for some reason eg need to have room for stencil right after depth */ - if (surf->flags & RADEON_SURF_ZBUFFER) { - surf->flags |= RADEON_SURF_SBUFFER; - } - /* set some default value to avoid sanity check choking on them */ surf->tile_split = 1024; surf->bankw = 1;