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[84.242.70.218]) by mx.google.com with ESMTPS id eu4sm2010809wib.2.2012.08.09.07.38.05 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 09 Aug 2012 07:38:06 -0700 (PDT) From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] radeon: force 2D tiling for MSAA surfaces Date: Thu, 9 Aug 2012 16:37:59 +0200 Message-Id: <1344523080-4420-1-git-send-email-maraeo@gmail.com> X-Mailer: git-send-email 1.7.9.5 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org --- radeon/radeon_surface.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) Reviewed-by: Jerome Glisse diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 874a092..499e994 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -154,7 +154,7 @@ static void surf_minify(struct radeon_surface *surf, surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->level[level].mode == RADEON_SURF_MODE_2D) { + if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) { surf->level[level].mode = RADEON_SURF_MODE_1D; return; @@ -382,6 +382,12 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man, unsigned mode; int r; + /* MSAA surfaces support the 2D mode only. */ + if (surf->nsamples > 1) { + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); + } + /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; @@ -401,6 +407,10 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man, /* force 1d on kernel that can't do 2d */ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { + if (surf->nsamples > 1) { + fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__); + return -EFAULT; + } mode = RADEON_SURF_MODE_1D; surf->flags = RADEON_SURF_CLR(surf->flags, MODE); surf->flags |= RADEON_SURF_SET(mode, MODE); @@ -548,7 +558,7 @@ static void eg_surf_minify(struct radeon_surface *surf, surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; - if (surf->level[level].mode == RADEON_SURF_MODE_2D) { + if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D) { if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) { surf->level[level].mode = RADEON_SURF_MODE_1D; return; @@ -687,6 +697,10 @@ static int eg_surface_sanity(struct radeon_surface_manager *surf_man, /* force 1d on kernel that can't do 2d */ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { + if (surf->nsamples > 1) { + fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface (%i).\n", __LINE__); + return -EFAULT; + } mode = RADEON_SURF_MODE_1D; surf->flags = RADEON_SURF_CLR(surf->flags, MODE); surf->flags |= RADEON_SURF_SET(mode, MODE); @@ -754,6 +768,12 @@ static int eg_surface_init(struct radeon_surface_manager *surf_man, unsigned mode; int r; + /* MSAA surfaces support the 2D mode only. */ + if (surf->nsamples > 1) { + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); + } + /* tiling mode */ mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;