diff mbox

[37/51] drm/i915: Pull intel_pipe_set_base() out of the crtc_mode_set() functions

Message ID 1351188354-24233-38-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Oct. 25, 2012, 6:05 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_pipe_set_base() (un)pins the buffers, so it can't be called from
the atomic modeset paths. Pull the intel_pipe_set_base() and watermark
modifications out of i9xx_crtc_mode_set() and ironlake_crtc_mode_set()
into intel_crtc_mode_set(), so that the former two can be used from the
atomic modeset paths.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   26 ++++++++++++--------------
 1 files changed, 12 insertions(+), 14 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f27ac4d..79b6de7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4387,7 +4387,6 @@  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	u32 dspcntr, pipeconf, vsyncshift;
 	bool ok, has_reduced_clock = false;
 	bool is_dp = false;
-	int ret;
 
 	ok = i9xx_compute_clocks(crtc, adjusted_mode, &clock,
 				 &has_reduced_clock, &reduced_clock,
@@ -4517,11 +4516,7 @@  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(DSPCNTR(plane), dspcntr);
 	POSTING_READ(DSPCNTR(plane));
 
-	ret = intel_pipe_set_base(crtc, x, y, fb);
-
-	intel_update_watermarks(dev);
-
-	return ret;
+	return 0;
 }
 
 /*
@@ -4795,7 +4790,6 @@  static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	bool ok, has_reduced_clock = false, is_sdvo = false;
 	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
 	struct intel_encoder *encoder, *edp_encoder = NULL;
-	int ret;
 	struct fdi_m_n m_n = {0};
 	u32 temp;
 	int target_clock, pixel_multiplier, lane, link_bw, factor;
@@ -5115,13 +5109,7 @@  static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
 	POSTING_READ(DSPCNTR(plane));
 
-	ret = intel_pipe_set_base(crtc, x, y, fb);
-
-	intel_update_watermarks(dev);
-
-	intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
-
-	return ret;
+	return 0;
 }
 
 int intel_check_clock(struct drm_crtc *crtc,
@@ -5164,6 +5152,16 @@  static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
 	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
 					      x, y, fb);
+
+	if (!ret) {
+		ret = intel_pipe_set_base(crtc, x, y, fb);
+
+		intel_update_watermarks(dev);
+
+		if (HAS_PCH_SPLIT(dev))
+			intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
+	}
+
 	drm_vblank_post_modeset(dev, pipe);
 
 	return ret;