From patchwork Mon Aug 12 18:19:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWFyZWsgT2zFocOhaw==?= X-Patchwork-Id: 2843244 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A92B1BF546 for ; Mon, 12 Aug 2013 18:31:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4E5972056E for ; Mon, 12 Aug 2013 18:31:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6B7C72055D for ; Mon, 12 Aug 2013 18:31:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 58429E771E for ; Mon, 12 Aug 2013 11:31:02 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-ea0-f181.google.com (mail-ea0-f181.google.com [209.85.215.181]) by gabe.freedesktop.org (Postfix) with ESMTP id 028A3E76DE for ; Mon, 12 Aug 2013 11:19:29 -0700 (PDT) Received: by mail-ea0-f181.google.com with SMTP id d10so3650743eaj.12 for ; Mon, 12 Aug 2013 11:19:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; bh=Mz9LM6WzhgGU97/Rja0t5Zg/MWpo+dbbZjb6sFMg7qg=; b=IEGvnJLG6WG+FboLEP/bufEydjAnD3S8f9VwJMUpIOGUU7p08H+Jy9VP70kkfoYvEq Uf3rDEBX1v8+79XvVEkIQpubXtcAsuV0FTwI5dQpDxb5A2ci8GgOsFdvt46uDDgE4a+u wvwA9J7HYdjWGA96NjhbkmXrvh3V+CtVCF7FNF1LmTUeGR8VVd653uUxUmL5TmdxMVsv sV0zttir7cDdgU4L+zaIH58Hde085bgZVVga5SniTHZ/dlrDib3YdKSuT/48y1iiotqB zMf8WnboFoeOUGBzvmhHDqTvK6VFU1997dv6CZNkdQkfK6RVP2yAE+OFrJMkKjU5icVH 2YPg== X-Received: by 10.14.219.198 with SMTP id m46mr366520eep.41.1376331569092; Mon, 12 Aug 2013 11:19:29 -0700 (PDT) Received: from localhost.localdomain ([194.228.11.33]) by mx.google.com with ESMTPSA id l47sm14804662eex.15.2013.08.12.11.19.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 11:19:28 -0700 (PDT) From: "=?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?=" To: xorg-driver-ati@lists.x.org, dri-devel@lists.freedesktop.org Subject: [PATCH] radeon/kms: set/get the scanout flag using the set/get_tiling ioctls Date: Mon, 12 Aug 2013 20:19:23 +0200 Message-Id: <1376331563-1244-1-git-send-email-marek.olsak@amd.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Basically just pass RADEON_TILING_R600_SCANOUT everywhere. Hopefully I didn't miss anything. This is only compile-tested. Signed-off-by: Marek Olšák --- src/drmmode_display.c | 44 +++++++++++++++++++++++++++++++++----------- src/radeon_bo_helper.c | 11 +++++++++-- src/radeon_drm.h | 5 +++-- src/radeon_kms.c | 28 +++++++++++++++++++--------- 4 files changed, 64 insertions(+), 24 deletions(-) diff --git a/src/drmmode_display.c b/src/drmmode_display.c index 3a0187e..7c055d3 100644 --- a/src/drmmode_display.c +++ b/src/drmmode_display.c @@ -123,7 +123,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn, surface->last_level = 0; surface->bpe = bpp / 8; surface->nsamples = 1; - surface->flags = RADEON_SURF_SCANOUT; + surface->flags = 0; /* we are requiring a recent enough libdrm version */ surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); @@ -136,6 +136,9 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn, surface->flags = RADEON_SURF_CLR(surface->flags, MODE); surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } + if (tiling & RADEON_TILING_R600_SCANOUT) { + surface->flags |= RADEON_SURF_SCANOUT; + } if (radeon_surface_best(info->surf_man, surface)) { return NULL; } @@ -313,6 +316,8 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode, struct radeon_bo *bo; drmModeFBPtr fbcon; struct drm_gem_flink flink; + unsigned tiling = 0; + RADEONInfoPtr info = RADEONPTR(pScrn); fbcon = drmModeGetFB(drmmode->fd, fbcon_id); if (fbcon == NULL) @@ -337,9 +342,13 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode, goto out_free_fb; } + if (info->ChipFamily >= CHIP_FAMILY_R600) { + tiling |= RADEON_TILING_R600_SCANOUT; + } + pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height, fbcon->depth, fbcon->bpp, - fbcon->pitch, 0, bo, NULL); + fbcon->pitch, tiling, bo, NULL); radeon_bo_unref(bo); out_free_fb: drmModeFreeFB(fbcon); @@ -399,6 +408,10 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode) drmmode_get_pitch_align(pScrn, info->pixel_bytes, tiling_flags)) * info->pixel_bytes; + if (info->ChipFamily >= CHIP_FAMILY_R600) { + tiling_flags |= RADEON_TILING_R600_SCANOUT; + } + dst = drmmode_create_bo_pixmap(pScrn, pScrn->virtualX, pScrn->virtualY, pScrn->depth, pScrn->bitsPerPixel, pitch, @@ -1418,6 +1431,10 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) tiling_flags |= RADEON_TILING_MACRO; } + if (info->ChipFamily >= CHIP_FAMILY_R600) { + tiling_flags |= RADEON_TILING_R600_SCANOUT; + } + pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(scrn, cpp, tiling_flags)) * cpp; height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, tiling_flags)); screen_size = RADEON_ALIGN(pitch * height, RADEON_GPU_PAGE_SIZE); @@ -1434,7 +1451,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) surface.last_level = 0; surface.bpe = cpp; surface.nsamples = 1; - surface.flags = RADEON_SURF_SCANOUT; + surface.flags = 0; /* we are requiring a recent enough libdrm version */ surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); @@ -1447,6 +1464,9 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } + if (tiling_flags & RADEON_TILING_R600_SCANOUT) { + surface.flags |= RADEON_SURF_SCANOUT; + } if (radeon_surface_best(info->surf_man, &surface)) { return FALSE; } @@ -1456,7 +1476,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) screen_size = surface.bo_size; base_align = surface.bo_alignment; pitch = surface.level[0].pitch_bytes; - tiling_flags = 0; + tiling_flags = RADEON_TILING_R600_SCANOUT; switch (surface.level[0].mode) { case RADEON_SURF_MODE_2D: tiling_flags |= RADEON_TILING_MACRO; @@ -1493,13 +1513,15 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) goto fail; #if X_BYTE_ORDER == X_BIG_ENDIAN - switch (cpp) { - case 4: - tiling_flags |= RADEON_TILING_SWAP_32BIT; - break; - case 2: - tiling_flags |= RADEON_TILING_SWAP_16BIT; - break; + if (info->ChipFamily < CHIP_FAMILY_R600) { + switch (cpp) { + case 4: + tiling_flags |= RADEON_TILING_SWAP_32BIT; + break; + case 2: + tiling_flags |= RADEON_TILING_SWAP_16BIT; + break; + } } #endif if (tiling_flags) diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c index 539590c..9ba7282 100644 --- a/src/radeon_bo_helper.c +++ b/src/radeon_bo_helper.c @@ -105,6 +105,10 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, tiling &= ~RADEON_TILING_MACRO; } + if (info->ChipFamily >= CHIP_FAMILY_R600) { + tiling |= RADEON_TILING_R600_SCANOUT; + } + heighta = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, tiling)); pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp; base_align = drmmode_get_base_align(pScrn, cpp, tiling); @@ -131,7 +135,7 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, */ tiling &= ~RADEON_TILING_MACRO; } - surface.flags = RADEON_SURF_SCANOUT; + surface.flags = 0; /* we are requiring a recent enough libdrm version */ surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); @@ -144,6 +148,9 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } + if (tiling & RADEON_TILING_R600_SCANOUT) { + surface.flags |= RADEON_SURF_SCANOUT; + } if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) { surface.flags |= RADEON_SURF_ZBUFFER; surface.flags |= RADEON_SURF_SBUFFER; @@ -157,7 +164,7 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth, size = surface.bo_size; base_align = surface.bo_alignment; pitch = surface.level[0].pitch_bytes; - tiling = 0; + tiling = RADEON_TILING_R600_SCANOUT; switch (surface.level[0].mode) { case RADEON_SURF_MODE_2D: tiling |= RADEON_TILING_MACRO; diff --git a/src/radeon_drm.h b/src/radeon_drm.h index 042e822..1fe3d50 100644 --- a/src/radeon_drm.h +++ b/src/radeon_drm.h @@ -802,8 +802,9 @@ struct drm_radeon_gem_create { #define RADEON_TILING_MACRO 0x1 #define RADEON_TILING_MICRO 0x2 -#define RADEON_TILING_SWAP_16BIT 0x4 -#define RADEON_TILING_SWAP_32BIT 0x8 +#define RADEON_TILING_R600_SCANOUT 0x4 /* r600 and later */ +#define RADEON_TILING_SWAP_16BIT 0x4 /* r100-r500 */ +#define RADEON_TILING_SWAP_32BIT 0x8 /* r100-r500 */ /* this object requires a surface when mapped - i.e. front buffer */ #define RADEON_TILING_SURFACE 0x10 #define RADEON_TILING_MICRO_SQUARE 0x20 diff --git a/src/radeon_kms.c b/src/radeon_kms.c index c3f50d5..87c5ca0 100644 --- a/src/radeon_kms.c +++ b/src/radeon_kms.c @@ -1477,6 +1477,11 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) } else tiling_flags |= RADEON_TILING_MACRO; } + + if (info->ChipFamily >= CHIP_FAMILY_R600) { + tiling_flags |= RADEON_TILING_R600_SCANOUT; + } + pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp; screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch; base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags); @@ -1497,7 +1502,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) surface.last_level = 0; surface.bpe = cpp; surface.nsamples = 1; - surface.flags = RADEON_SURF_SCANOUT; + surface.flags = 0; /* we are requiring a recent enough libdrm version */ surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX; surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); @@ -1510,6 +1515,9 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) surface.flags = RADEON_SURF_CLR(surface.flags, MODE); surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); } + if (tiling_flags & RADEON_TILING_R600_SCANOUT) { + surface.flags |= RADEON_SURF_SCANOUT; + } if (radeon_surface_best(info->surf_man, &surface)) { xf86DrvMsg(pScreen->myNum, X_ERROR, "radeon_surface_best failed\n"); @@ -1523,7 +1531,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) pitch = surface.level[0].pitch_bytes; screen_size = surface.bo_size; base_align = surface.bo_alignment; - tiling_flags = 0; + tiling_flags = RADEON_TILING_R600_SCANOUT; switch (surface.level[0].mode) { case RADEON_SURF_MODE_2D: tiling_flags |= RADEON_TILING_MACRO; @@ -1577,13 +1585,15 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) } } #if X_BYTE_ORDER == X_BIG_ENDIAN - switch (cpp) { - case 4: - tiling_flags |= RADEON_TILING_SWAP_32BIT; - break; - case 2: - tiling_flags |= RADEON_TILING_SWAP_16BIT; - break; + if (info->ChipFamily < CHIP_FAMILY_R600) { + switch (cpp) { + case 4: + tiling_flags |= RADEON_TILING_SWAP_32BIT; + break; + case 2: + tiling_flags |= RADEON_TILING_SWAP_16BIT; + break; + } } #endif if (tiling_flags)