diff mbox

[2/3] ARM: dts: arndale: Add hdmi phy settings

Message ID 1376377771-9325-3-git-send-email-s.shirish@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Shirish S Aug. 13, 2013, 7:09 a.m. UTC 
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.

Signed-off-by: Shirish S <s.shirish@samsung.com>
---
 arch/arm/boot/dts/exynos5250-arndale.dts |  120 ++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)
diff mbox

Patch

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..59db48a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,126 @@ 
 
 	hdmi {
 		hpd-gpio = <&gpx3 7 2>;
+		hdmiphy_confs {
+			nr_confs = <13>;
+			conf0: conf0 {
+				clock-frequency = <25200000>;
+				conf =  /bits/ 8 <
+					0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+					0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf1: conf1 {
+				clock-frequency = <27000000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+					0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+					0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf2: conf2 {
+				clock-frequency = <27027000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+					0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+				>;
+			};
+			conf3: conf3 {
+				clock-frequency = <36000000>;
+				conf =  /bits/ 8 <
+					0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+					0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf4: conf4 {
+				clock-frequency = <40000000>;
+				conf = /bits/ 8  <
+					0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+					0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf5: conf5 {
+				clock-frequency = <65000000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+					0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf6: conf6 {
+				clock-frequency = <74176000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+					0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+					0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf7: conf7 {
+				clock-frequency = <74250000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+					0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+					0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+				>;
+			};
+			conf8: conf8 {
+				clock-frequency = <83500000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x23 0x11 0x40 0x0c 0xfb 0x08
+					0x85 0xa0 0xd1 0xd8 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0x93 0x24 0x01 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf9: conf9 {
+				clock-frequency = <106500000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x2c 0x12 0x40 0x0c 0x09 0x08
+					0x84 0xa0 0x0a 0xd9 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0x73 0x24 0x01 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf10: conf10 {
+				clock-frequency = <108000000>;
+				conf = /bits/ 8  <
+					0x01 0x51 0x2d 0x15 0x40 0x01 0x00 0x08
+					0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0xc7 0x25 0x03 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf11: conf11 {
+				clock-frequency = <146250000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x3d 0x15 0x40 0x18 0xfd 0x08
+					0x83 0xa0 0x6e 0xd9 0x45 0xa0 0xac 0x80
+					0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0x50 0x25 0x03 0x00 0x00 0x01 0x80
+				>;
+			};
+			conf12: conf12 {
+				clock-frequency = <148500000>;
+				conf = /bits/ 8  <
+					0x01 0xd1 0x1f 0x00 0x40 0x40 0xf8 0x08
+					0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+					0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+					0x54 0x4b 0x25 0x03 0x00 0x00 0x01 0x00
+				>;
+			};
+		};
 		vdd_osc-supply = <&ldo10_reg>;
 		vdd_pll-supply = <&ldo8_reg>;
 		vdd-supply = <&ldo8_reg>;