From patchwork Tue Aug 13 08:14:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shirish S X-Patchwork-Id: 2843756 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 88D13BF546 for ; Tue, 13 Aug 2013 15:17:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2308920424 for ; Tue, 13 Aug 2013 15:17:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AE06C203F7 for ; Tue, 13 Aug 2013 15:17:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BE27E7669 for ; Tue, 13 Aug 2013 08:17:56 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by gabe.freedesktop.org (Postfix) with ESMTP id CEE6AE78AA for ; Tue, 13 Aug 2013 00:52:12 -0700 (PDT) Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRG00JOALUQENI0@mailout1.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 13 Aug 2013 16:52:07 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 6E.25.11618.7A5E9025; Tue, 13 Aug 2013 16:52:07 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-9b-5209e5a78aa1 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 1E.A9.32250.7A5E9025; Tue, 13 Aug 2013 16:52:07 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRG00K7WLUMS6D0@mmp1.samsung.com>; Tue, 13 Aug 2013 16:52:07 +0900 (KST) From: Shirish S To: dri-devel@lists.freedesktop.org, inki.dae@samsung.com Subject: [PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings Date: Tue, 13 Aug 2013 13:44:21 +0530 Message-id: <1376381661-28847-4-git-send-email-s.shirish@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1376381661-28847-1-git-send-email-s.shirish@samsung.com> References: <1376381661-28847-1-git-send-email-s.shirish@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRmVeSWpSXmKPExsWyRsSkRnf5U84ggwnbFSx6z51ksrjy9T2b xaT7E1gsmnYcZHNg8ZjdcJHFY/u3B6we97uPM3n0bVnFGMASxWWTkpqTWZZapG+XwJWxYfos xoL9LhX9h+saGJtNuxg5OSQETCReXW5gg7DFJC7cWw9kc3EICSxllPjz8x0LTNHbyfPZIRKL GCU2zWqCcmYzSexc94AdpIpNQF3i4uTVzCC2iIClxIOtv8FsZgEtiUd7d7GC2MIC3hKndixi 6mLk4GARUJU4dcgWJMwr4Crx4XIj1DJFie5nE8Au4hRwk1j7aSkbSLkQUM2KjbogayUE/rNJ fPl9DWw8i4CAxLfJh1hAaiQEZCU2HWCGGCMpcXDFDZYJjMILGBlWMYqmFiQXFCelF5nqFSfm Fpfmpesl5+duYgQG7+l/zybuYLx/wPoQYzLQuInMUqLJ+cDgzyuJNzQ2M7IwNTE1NjK3NCNN WEmcV73FOlBIID2xJDU7NbUgtSi+qDQntfgQIxMHp1QD41LZ8t5Dlh+vvNnNmrMzZXnAnP5N H26lvfA/fnh/sfVVRpV7N6+vXfRRpt5YvWrXuiV7ppvn7lloaxu9ekLQb5XL8s3fEu86bDr1 2XtTkrTEe5EqT6+qA78keKdeFs4MN2hNzTTnD56wlbf+WdSG6+lT91UH90zUinU5EDv74NW/ 1x5kr+/dH67EUpyRaKjFXFScCAC7REWddAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsVy+t9jAd3lTzmDDHreiln0njvJZHHl63s2 i0n3J7BYNO04yObA4jG74SKLx/ZvD1g97ncfZ/Lo27KKMYAlqoHRJiM1MSW1SCE1Lzk/JTMv 3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwdoqZJCWWJOKVAoILG4WEnfDtOE0BA3 XQuYxghd35AguB4jAzSQsIYxY8P0WYwF+10q+g/XNTA2m3YxcnJICJhIvJ08nx3CFpO4cG89 WxcjF4eQwCJGiU2zmtghnNlMEjvXPQCrYhNQl7g4eTUziC0iYCnxYOtvMJtZQEvi0d5drCC2 sIC3xKkdi5i6GDk4WARUJU4dsgUJ8wq4Sny43MgCsUxRovvZBDYQm1PATWLtp6VsIOVCQDUr NupOYORdwMiwilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyM4Np5J7WBc2WBxiFGAg1GJh1fg PUeQEGtiWXFl7iFGCQ5mJRHekzqcQUK8KYmVValF+fFFpTmpxYcYk4FumsgsJZqcD4zbvJJ4 Q2MTc1NjU0sTCxMzS9KElcR5D7RaBwoJpCeWpGanphakFsFsYeLglGpgzL3A1Hzky8RY74Yq jXCm6Yv6mfdvj49NXvr0yu6d/Jb/zd0uF1tNrfL9E/FInfVo3oLwDTP7lM4wNj4Jz9/tvjRI P2rij65vN31XLM+rml+29GLdrL1/NrLW/7raVXp6akGzct05rzqOnouret0YVsrNu3iroaD6 ktDO1raAn1f4grjXGtXdVmIpzkg01GIuKk4EAPbzfdjRAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Tue, 13 Aug 2013 08:09:57 -0700 Cc: shirish@chromium.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds dt support to hdmiphy config settings as it is board specific and depends on the signal pattern of board. Signed-off-by: Shirish S --- .../devicetree/bindings/video/exynos_hdmi.txt | 18 +- drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++++++------------- 2 files changed, 80 insertions(+), 129 deletions(-) diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 323983b..fb8a643 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -12,7 +12,11 @@ Required properties: a) phandle of the gpio controller node. b) pin number within the gpio controller. c) optional flags and pull up/down. - +- hdmiphy_confs: following information about the hdmiphy conf settings. + a) "nr_confs" specifies the number of pixel clocks supported. + b) "confX: confX" specifies the phy configuration settings, + "clock-frequency" specifies the pixel clock + "conf" specifies the setting for the corresponding pixel clock Example: hdmi { @@ -20,4 +24,16 @@ Example: reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 1>; + hdmiphy_confs { + nr_confs = <1>; + conf0: conf0 { + clock-frequency = <25200000>; + conf = /bits/ 8 < + 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08 + 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + } }; diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 2f5c694..cb929ff 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -179,6 +179,11 @@ struct hdmi_conf_regs { } conf; }; +struct hdmiphy_config { + int pixel_clock; + u8 conf[32]; +}; + struct hdmi_context { struct device *dev; struct drm_device *drm_dev; @@ -199,16 +204,14 @@ struct hdmi_context { struct hdmi_resources res; + struct hdmiphy_config *confs; + int nr_confs; + int hpd_gpio; enum hdmi_type type; }; -struct hdmiphy_config { - int pixel_clock; - u8 conf[32]; -}; - /* list of phy config settings */ static const struct hdmiphy_config hdmiphy_v13_configs[] = { { @@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { }, }; -static const struct hdmiphy_config hdmiphy_v14_configs[] = { - { - .pixel_clock = 25200000, - .conf = { - 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08, - 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 27000000, - .conf = { - 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20, - 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80, - 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 27027000, - .conf = { - 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08, - 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, - }, - }, - { - .pixel_clock = 36000000, - .conf = { - 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08, - 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 40000000, - .conf = { - 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08, - 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 65000000, - .conf = { - 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08, - 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 74176000, - .conf = { - 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08, - 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 74250000, - .conf = { - 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08, - 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, - 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, - }, - }, - { - .pixel_clock = 83500000, - .conf = { - 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08, - 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 106500000, - .conf = { - 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, - 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 108000000, - .conf = { - 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08, - 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 146250000, - .conf = { - 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08, - 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, - 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, - }, - }, - { - .pixel_clock = 148500000, - .conf = { - 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08, - 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, - 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, - }, - }, -}; - struct hdmi_infoframe { enum HDMI_PACKET_TYPE type; u8 ver; @@ -777,8 +660,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) confs = hdmiphy_v13_configs; count = ARRAY_SIZE(hdmiphy_v13_configs); } else if (hdata->type == HDMI_TYPE14) { - confs = hdmiphy_v14_configs; - count = ARRAY_SIZE(hdmiphy_v14_configs); + confs = hdata->confs; + count = hdata->nr_confs; } else return -EINVAL; @@ -1365,7 +1248,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) if (hdata->type == HDMI_TYPE13) hdmiphy_data = hdmiphy_v13_configs[i].conf; else - hdmiphy_data = hdmiphy_v14_configs[i].conf; + hdmiphy_data = hdata->confs[i].conf; memcpy(buffer, hdmiphy_data, 32); ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); @@ -1885,6 +1768,51 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata err_data: return NULL; } + +static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev, + struct hdmi_context *hdata) +{ + struct device *dev = &pdev->dev; + struct device_node *dev_np = dev->of_node; + struct device_node *phy_conf, *cfg_np; + int i = 0; + + phy_conf = of_find_node_by_name(dev_np, "hdmiphy_confs"); + if (phy_conf == NULL) { + DRM_ERROR("Did not find hdmiphy_conf node\n"); + return -ENODEV; + } + + of_property_read_u32(phy_conf, "nr_confs", &hdata->nr_confs); + hdata->confs = kzalloc((hdata->nr_confs * sizeof + (struct hdmiphy_config)), GFP_KERNEL); + + for_each_child_of_node(phy_conf, cfg_np) { + if (!of_find_property(cfg_np, "clock-frequency", NULL)) + continue; + + if (of_property_read_u32_array(cfg_np, "clock-frequency", + (u32 *)&hdata->confs[i]. + pixel_clock, 1)) { + DRM_ERROR("Failed to get pixel clock\n"); + return -EINVAL; + } + + /* + * conf property holds the phy setting value + * for a particular board + */ + if (of_property_read_u8_array(cfg_np, "conf", + (u8 *)&hdata->confs[i].conf, 32)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + i++; + } + return 0; + +} + #else static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata (struct device *dev) @@ -2038,6 +1966,13 @@ static int hdmi_probe(struct platform_device *pdev) goto err_hdmiphy; } + /* get hdmiphy confs */ + ret = drm_hdmi_dt_parse_phy_conf(pdev, hdata); + if (ret) { + DRM_ERROR("failed to get confs\n"); + goto err_hdmiphy; + } + /* Attach HDMI Driver to common hdmi. */ exynos_hdmi_drv_attach(drm_hdmi_ctx);