From patchwork Wed Aug 28 15:48:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 2850914 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DE36DBF546 for ; Wed, 28 Aug 2013 16:36:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D960C20543 for ; Wed, 28 Aug 2013 16:36:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A9E7D2053D for ; Wed, 28 Aug 2013 16:36:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E919E72E9 for ; Wed, 28 Aug 2013 09:36:56 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from hqemgate14.nvidia.com (hqemgate14.nvidia.com [216.228.121.143]) by gabe.freedesktop.org (Postfix) with ESMTP id 298CFE7AB0 for ; Wed, 28 Aug 2013 08:48:53 -0700 (PDT) Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 28 Aug 2013 08:48:29 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 28 Aug 2013 08:46:21 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 28 Aug 2013 08:46:21 -0700 Received: from deemhub01.nvidia.com (10.21.69.137) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 28 Aug 2013 08:48:14 -0700 Received: from mperttunen-lnx.Nvidia.com (10.21.65.27) by deemhub01.nvidia.com (10.21.69.137) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 28 Aug 2013 17:48:11 +0200 From: Mikko Perttunen To: Subject: [PATCH v2 3/6] host1x: hdmi: Enable Vdd earlier for hotplug/DDC Date: Wed, 28 Aug 2013 18:48:39 +0300 Message-ID: <1377704922-2824-4-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1377704922-2824-1-git-send-email-mperttunen@nvidia.com> References: <1377704922-2824-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 28 Aug 2013 09:30:36 -0700 Cc: linux-tegra@vger.kernel.org, tbergstrom@nvidia.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Mikko Perttunen X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org Errors-To: dri-devel-bounces+patchwork-dri-devel=patchwork.kernel.org@lists.freedesktop.org X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Vdd regulator used to be enabled only at tegra_output_hdmi_enable, which is called after a sink is detected. However, the HDMI hotplug pin works by returning the voltage supplied by the Vdd pin, so this meant that the hotplug pin was never asserted and the sink was not detected unless the Vdd regulator was set to be always on. This patch moves the enable to the tegra_hdmi_drm_init function to make sure the regulator will get enabled. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/drm/hdmi.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/host1x/drm/hdmi.c b/drivers/gpu/host1x/drm/hdmi.c index 140339b..96a6ae1 100644 --- a/drivers/gpu/host1x/drm/hdmi.c +++ b/drivers/gpu/host1x/drm/hdmi.c @@ -716,12 +716,6 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) h_back_porch = mode->htotal - mode->hsync_end; h_front_porch = mode->hsync_start - mode->hdisplay; - err = regulator_enable(hdmi->vdd); - if (err < 0) { - dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); - return err; - } - err = regulator_enable(hdmi->pll); if (err < 0) { dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); @@ -943,7 +937,6 @@ static int tegra_output_hdmi_disable(struct tegra_output *output) tegra_periph_reset_assert(hdmi->clk); clk_disable(hdmi->clk); regulator_disable(hdmi->pll); - regulator_disable(hdmi->vdd); return 0; } @@ -1240,6 +1233,12 @@ static int tegra_hdmi_drm_init(struct host1x_client *client, struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); int err; + err = regulator_enable(hdmi->vdd); + if (err < 0) { + dev_err(client->dev, "vdd regulator enable failed: %d\n", err); + return err; + } + hdmi->output.type = TEGRA_OUTPUT_HDMI; hdmi->output.dev = client->dev; hdmi->output.ops = &hdmi_ops; @@ -1283,6 +1282,8 @@ static int tegra_hdmi_drm_exit(struct host1x_client *client) return err; } + regulator_disable(hdmi->vdd); + return 0; }