From patchwork Mon Oct 28 06:24:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shirish S X-Patchwork-Id: 3107311 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7065F9F2B7 for ; Tue, 29 Oct 2013 10:31:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2CEAB20170 for ; Tue, 29 Oct 2013 10:31:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1328820142 for ; Tue, 29 Oct 2013 10:31:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E8270EEAAA; Tue, 29 Oct 2013 03:28:00 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by gabe.freedesktop.org (Postfix) with ESMTP id 26C1CE6212 for ; Sun, 27 Oct 2013 23:04:12 -0700 (PDT) Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MVD000SS7IKOXR0@mailout2.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 28 Oct 2013 15:04:08 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 38.85.10672.85EFD625; Mon, 28 Oct 2013 15:04:08 +0900 (KST) X-AuditID: cbfee68d-b7fa16d0000029b0-46-526dfe58072a Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 5F.D4.09687.85EFD625; Mon, 28 Oct 2013 15:04:08 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MVD00HBE7IMA380@mmp1.samsung.com>; Mon, 28 Oct 2013 15:04:08 +0900 (KST) From: Shirish S To: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, devicetree@vger.kernel.org Subject: [PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings Date: Mon, 28 Oct 2013 11:54:22 +0530 Message-id: <1382941462-6691-4-git-send-email-s.shirish@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1382941462-6691-1-git-send-email-s.shirish@samsung.com> References: <1382941462-6691-1-git-send-email-s.shirish@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsWyRsSkTjfiX26QwYu7Ghbzj5xjtbjy9T2b xaT7E1gsps3eyGhxd8NZRoumHQfZLGZMfsnmwO4xu+Eii8f97uNMHn1bVjF6fN4kF8ASxWWT kpqTWZZapG+XwJVxfO415oJHBhXH16xibGD8qtbFyMkhIWAiMf3HDhYIW0ziwr31bF2MXBxC AksZJR4ebGWEKXq5aQNUYhGjxKKLU1hBEkICs5kkjn3XArHZBNQlLk5ezQxiiwiES0zd8xfM ZhbIkdg67y5YvbCAt8SpHYuYQGwWAVWJUxcus4HYvAIuEn8XX2CHWKYo0f1sAlicU8BVYm7b CmaIXS4SH1tfMIIcISHQzy7xf+psqEECEt8mHwJ6gQMoISux6QAzxBxJiYMrbrBMYBRewMiw ilE0tSC5oDgpvchQrzgxt7g0L10vOT93EyMwuE//e9a7g/H2AetDjMlA4yYyS4km5wOjI68k 3tDYzMjC1MTU2Mjc0ow0YSVx3qSHSUFCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGE8pnd4u Hil4vuX8Nj2DI1N3Fxw4u+xF0LED/Au3F8ff4Zy29+TeQ5lcCgff9F06vyNs7lQH88M3px3S Lp0fuD7ImvXGEVfxaMu2O9+f988/JK4ze5d8TuGTV4aWs/p7PKZsZv/tel/h/l/uZfNOB36L vszq5bqhw9Pr/BSRqy1PRS6ue5Y9LWyhEktxRqKhFnNRcSIADcSXcoQCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHIsWRmVeSWpSXmKPExsVy+t9jAd2If7lBBvtuyFvMP3KO1eLK1/ds FpPuT2CxmDZ7I6PF3Q1nGS2adhxks5gx+SWbA7vH7IaLLB73u48zefRtWcXo8XmTXABLVAOj TUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7QCUoKZYk5 pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjONzrzEXPDKoOL5mFWMD41e1LkZO DgkBE4mXmzawQdhiEhfurQeyuTiEBBYxSiy6OIUVJCEkMJtJ4th3LRCbTUBd4uLk1cwgtohA uMTUPX/BbGaBHImt8+6C1QsLeEuc2rGICcRmEVCVOHXhMtgCXgEXib+LL7BDLFOU6H42ASzO KeAqMbdtBTPELheJj60vGCcw8i5gZFjFKJpakFxQnJSea6hXnJhbXJqXrpecn7uJERw7z6R2 MK5ssDjEKMDBqMTDu2FtbpAQa2JZcWXuIUYJDmYlEd6+W0Ah3pTEyqrUovz4otKc1OJDjMlA V01klhJNzgfGdV5JvKGxibmpsamliYWJmSVpwkrivAdarQOFBNITS1KzU1MLUotgtjBxcEo1 MPYveSSmorNke0JHv97HbkHFKfeqX086+cEuyXNj3qemsNtH6r/fzte/d+/w/qSDHFWufJ6B Pb+l1899eGsK95Lzq998tQ60EnDrTXQ2q+Y08nQsm+EXKMuh/qJoYb0U20LXGqXqxz7SzyVn B/9hFnf9/th1bUSHTlnP41MqSu+fZdu+uM6grsRSnJFoqMVcVJwIAPp17GThAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Mailman-Approved-At: Tue, 29 Oct 2013 03:25:41 -0700 Cc: sw0312.kim@samsung.com, shirish@chromium.org, Shirish S X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds dt support to hdmiphy config settings as it is board specific and depends on the signal pattern of board. Signed-off-by: Shirish S --- .../devicetree/bindings/video/exynos_hdmi.txt | 29 ++++++++ arch/arm/boot/dts/exynos5250-arndale.dts | 6 +- drivers/gpu/drm/exynos/exynos_hdmi.c | 70 ++++++++++++++++++-- 3 files changed, 98 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 323983b..770f92d 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -13,6 +13,27 @@ Required properties: b) pin number within the gpio controller. c) optional flags and pull up/down. +- hdmiphy-confs: following information about the hdmiphy conf settings. + a) "nr-confs" specifies the number of pixel clocks supported. + b) "confX: confX" specifies the phy configuration settings, + "clock-frequency" specifies the pixel clock + "con-de-emphasis-level" specifies the configuration + of Data De-emphasis levels. + 0x145D0040h[3:0] permitted values: + 0000 means 760 mVdiff && 1111 means 1400 mVdiff + 0x145D0040h[7:4] permitted values: + 000 0dB + 0001 -0.25dB + 0010 -0.7dB + 0011 -1.15dB + 1111 -7.45dB + "con-clock-level" specifies the configuration for + the corresponding clock level. + 0x145D005Ch [1:0] permitted values: + 00 means 0 mVdiff && 11 means 60 mVdiff + 0x145D005Ch [7:3] permitted values: + 00000 is 790 mVdiff + 11111 is 1430 mVdiff Example: hdmi { @@ -20,4 +41,12 @@ Example: reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 1>; + hdmiphy-confs { + nr-confs = <1>; + conf0: conf0 { + clock-frequency = <25200000>; + conf-de-emphasis-level = /bits/ 8 <0x26>; + conf-clock-level = /bits/ 8 < 0x66>; + }; + } }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index c23f16b..436b75a 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -424,6 +424,9 @@ hdmi { hpd-gpio = <&gpx3 7 2>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; hdmiphy-confs { nr-confs = <13>; conf0: conf0 { @@ -492,9 +495,6 @@ conf-clock-level = /bits/ 8 < 0x66>; }; }; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; }; mmc_reg: voltage-regulator { diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index a0e10ae..3125e67 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -200,6 +200,9 @@ struct hdmi_context { struct hdmi_resources res; + struct hdmiphy_config *confs; + int nr_confs; + int hpd_gpio; enum hdmi_type type; @@ -259,7 +262,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { }, }; -static const struct hdmiphy_config hdmiphy_v14_configs[] = { +static struct hdmiphy_config hdmiphy_v14_configs[] = { { .pixel_clock = 25200000, .conf = { @@ -778,8 +781,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) confs = hdmiphy_v13_configs; count = ARRAY_SIZE(hdmiphy_v13_configs); } else if (hdata->type == HDMI_TYPE14) { - confs = hdmiphy_v14_configs; - count = ARRAY_SIZE(hdmiphy_v14_configs); + confs = hdata->confs; + count = hdata->nr_confs; } else return -EINVAL; @@ -1366,7 +1369,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) if (hdata->type == HDMI_TYPE13) hdmiphy_data = hdmiphy_v13_configs[i].conf; else - hdmiphy_data = hdmiphy_v14_configs[i].conf; + hdmiphy_data = hdata->confs[i].conf; memcpy(buffer, hdmiphy_data, 32); ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); @@ -1858,6 +1861,56 @@ void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy) hdmi_hdmiphy = hdmiphy; } +static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev, + struct hdmi_context *hdata) +{ + struct device *dev = &pdev->dev; + struct device_node *dev_np = dev->of_node; + struct device_node *phy_conf, *cfg_np; + int i = 0; + + phy_conf = of_find_node_by_name(dev_np, "hdmiphy-confs"); + if (phy_conf == NULL) { + DRM_ERROR("Did not find hdmiphy_conf node\n"); + return -ENODEV; + } + + of_property_read_u32(phy_conf, "nr-confs", &hdata->nr_confs); + hdata->confs = kzalloc((hdata->nr_confs * sizeof + (struct hdmiphy_config)), GFP_KERNEL); + + /* Initialize with default config */ + hdata->confs = hdmiphy_v14_configs; + + for_each_child_of_node(phy_conf, cfg_np) { + if (!of_find_property(cfg_np, "clock-frequency", NULL)) + continue; + + if (of_property_read_u32_array(cfg_np, "clock-frequency", + (u32 *)&hdata->confs[i]. + pixel_clock, 1)) { + DRM_ERROR("Failed to get pixel clock\n"); + return -EINVAL; + } + + /* Overwrite the data de-emphasis and data level */ + if (of_property_read_u8_array(cfg_np, "conf-de-emphasis-level", + (u8 *)&hdata->confs[i].conf[16], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + /* Overwrite the clock level diff */ + if (of_property_read_u8_array(cfg_np, "conf-clock-level", + (u8 *)&hdata->confs[i].conf[23], 1)) { + DRM_ERROR("Failed to get conf\n"); + return -EINVAL; + } + i++; + } + return 0; + +} + static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata (struct device *dev) { @@ -1986,6 +2039,15 @@ static int hdmi_probe(struct platform_device *pdev) goto err_hdmiphy; } + /* get hdmiphy confs */ + if (hdata->type == HDMI_TYPE14) { + ret = drm_hdmi_dt_parse_phy_conf(pdev, hdata); + if (ret) { + DRM_ERROR("failed to get confs\n"); + goto err_hdmiphy; + } + } + /* Attach HDMI Driver to common hdmi. */ exynos_hdmi_drv_attach(drm_hdmi_ctx);