From patchwork Fri Nov 15 17:55:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWFyZWsgT2zFocOhaw==?= X-Patchwork-Id: 3189381 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BEC3AC045B for ; Fri, 15 Nov 2013 17:55:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D5C1520930 for ; Fri, 15 Nov 2013 17:55:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EECD320925 for ; Fri, 15 Nov 2013 17:55:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D7ED4FB967; Fri, 15 Nov 2013 09:55:37 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-ea0-f169.google.com (mail-ea0-f169.google.com [209.85.215.169]) by gabe.freedesktop.org (Postfix) with ESMTP id 01929FB961 for ; Fri, 15 Nov 2013 09:55:33 -0800 (PST) Received: by mail-ea0-f169.google.com with SMTP id l9so1177147eaj.28 for ; Fri, 15 Nov 2013 09:55:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; bh=B+/JiXgO2t/5UfC1Gekws3Ff8ZLZCocqry2ERqa2ptg=; b=DrmJwJN9ZoaHWDZqFQFkiW5sJuzr/6WM4MokfcWF7U2D2lQ7tOkGYGrFl9B9GFupzb 1FUqS8YKcju9/XCNFKxfy2gpdQ3hBr+fMVuScOI6xHRK2nG79Twa1tKkhl6Cw1/IjZKs FU+c2VUvCufhQljOheSincShfKeqCWcwZ59dqTlmoiajsXVuhz4JmJxm9ov0xgff90hb lDhCOQKLsby+doe+IwYQGoL77BQqEroQ+a1n4KPAf2hioo8u7EGFDphw1xDy7t1ms9c+ eBms0pdOd0yhKMz5X85XH+gybnE8wiHKE7By7N9nGsyNlaonszDxv0AF9BI5D1my4tso XLsg== X-Received: by 10.14.5.133 with SMTP id 5mr1127595eel.84.1384538133164; Fri, 15 Nov 2013 09:55:33 -0800 (PST) Received: from peklo.amd.com ([194.228.11.93]) by mx.google.com with ESMTPSA id g8sm8441602eep.20.2013.11.15.09.55.32 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 15 Nov 2013 09:55:32 -0800 (PST) From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] radeon: fix mipmap level 0 and 1 alignment for SI and CIK Date: Fri, 15 Nov 2013 18:55:26 +0100 Message-Id: <1384538127-11532-1-git-send-email-maraeo@gmail.com> X-Mailer: git-send-email 1.8.3.2 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Michel Dänzer Signed-off-by: Marek Olšák --- radeon/radeon_surface.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index d5c45c4..56e2e4a 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -1540,6 +1540,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man, uint64_t offset, unsigned start_level) { uint32_t xalign, yalign, zalign, slice_align; + unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); unsigned i; /* compute alignment */ @@ -1551,11 +1552,11 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man, xalign = MAX2((bpe == 1) ? 64 : 32, xalign); } - if (!start_level) { - surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + if (start_level <= 1) { + surf->bo_alignment = MAX2(surf->bo_alignment, alignment); if (offset) { - offset = ALIGN(offset, surf->bo_alignment); + offset = ALIGN(offset, alignment); } } @@ -1566,7 +1567,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man, /* level0 and first mipmap need to have alignment */ offset = surf->bo_size; if ((i == 0)) { - offset = ALIGN(offset, surf->bo_alignment); + offset = ALIGN(offset, alignment); } if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { if (surf->level == level) { @@ -1608,6 +1609,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, uint64_t offset, unsigned start_level) { + uint64_t aligned_offset = offset; unsigned tilew, tileh, tileb; unsigned mtilew, mtileh, mtileb; unsigned slice_pt; @@ -1631,19 +1633,19 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, /* macro tile bytes */ mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb; - if (!start_level) { + if (start_level <= 1) { unsigned alignment = MAX2(256, mtileb); surf->bo_alignment = MAX2(surf->bo_alignment, alignment); - if (offset) { - offset = ALIGN(offset, alignment); + if (aligned_offset) { + aligned_offset = ALIGN(aligned_offset, alignment); } } /* build mipmap tree */ for (i = start_level; i <= surf->last_level; i++) { level[i].mode = RADEON_SURF_MODE_2D; - si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, offset); + si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset); if (level[i].mode == RADEON_SURF_MODE_1D) { switch (tile_mode) { case SI_TILE_MODE_COLOR_2D_8BPP: @@ -1657,10 +1659,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT; break; case SI_TILE_MODE_DEPTH_STENCIL_2D: - if (surf_man->family >= CHIP_BONAIRE) - tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D; - else - tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; + tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D; break; default: return -EINVAL; @@ -1668,9 +1667,9 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man, return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); } /* level0 and first mipmap need to have alignment */ - offset = surf->bo_size; + aligned_offset = surf->bo_size; if ((i == 0)) { - offset = ALIGN(offset, surf->bo_alignment); + aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); } if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { if (surf->level == level) {