From patchwork Tue Apr 15 05:47:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YoungJun Cho X-Patchwork-Id: 3988911 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 09D22BFF02 for ; Tue, 15 Apr 2014 05:47:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 37FC820251 for ; Tue, 15 Apr 2014 05:47:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4FD4620211 for ; Tue, 15 Apr 2014 05:47:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 121E06E17D; Mon, 14 Apr 2014 22:47:54 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by gabe.freedesktop.org (Postfix) with ESMTP id D2BE66E17D for ; Mon, 14 Apr 2014 22:47:52 -0700 (PDT) Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N4200KCL5FPR500@mailout4.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 15 Apr 2014 14:47:50 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.45]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 8D.8B.09028.508CC435; Tue, 15 Apr 2014 14:47:49 +0900 (KST) X-AuditID: cbfee68e-b7f566d000002344-cd-534cc805b65d Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 5F.DC.28157.508CC435; Tue, 15 Apr 2014 14:47:49 +0900 (KST) Received: from localhost.localdomain ([10.252.75.90]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N4200KNL5FIU632@mmp1.samsung.com>; Tue, 15 Apr 2014 14:47:49 +0900 (KST) From: YoungJun Cho To: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [RFC PATCH 02/14] drm/exynos: dsi: delay setting clocks after reset Date: Tue, 15 Apr 2014 14:47:30 +0900 Message-id: <1397540862-21359-3-git-send-email-yj44.cho@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1397540862-21359-1-git-send-email-yj44.cho@samsung.com> References: <1397540862-21359-1-git-send-email-yj44.cho@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsVy+t8zXV3WEz7BBle3mVncWneO1aL33Ekm i/lHgKwrX9+zWfS/Wchqce7VSkaLSfcnsFi8uHeRxaJ3wVU2i7NNb9gtZpzfx2Sx9PpFJosJ 09eyWLTuPQIUm/ySzeLnrnksDgIea+atYfS43NfL5LFz1l12j5XLv7B5bFrVyeax/dsDVo/7 3ceZPPq2rGL0+LxJLoAzissmJTUnsyy1SN8ugStj1flWloKH7BVtP2oaGC+xdTFyckgImEgs 72yFssUkLtxbD2RzcQgJLGOUON48Aa7o1ooTjBCJRYwSb14eYodwWpkkXv69ClbFJqAp8fzj DlYQW0TAVKJj0lIWkCJmgSdMEl3X+plAEsICPhJfmhrAbBYBVYlVxz4wg9i8Ai4SP1++Bmrg AFqnIDFnkg1ImFPAVeLq9gVgYSGgksXLCkFGSgj8ZJe4u/UmI8QYAYlvkw9BtcpKbDrADHG0 pMTBFTdYJjAKL2BkWMUomlqQXFCclF5kpFecmFtcmpeul5yfu4kREmd9OxhvHrA+xJgMNG4i s5Rocj4wTvNK4g2NzYwsTE1MjY3MLc1IE1YS5130MClISCA9sSQ1OzW1ILUovqg0J7X4ECMT B6dUA6PT5sf3ek5oN5c0XBDmqi/jvjyZ5dTzeOaNb5/eCdb3fBWg9dmOKXXjm+ktX49OyNtt 3zmrZh5PocqTaE/Hx6+OfJRleBv0pTL3PJff932BDbe3dD4PlvrXd/Rc4Cr93zorNqduzpjf /z+g39DsrzNbkG7ZtXOv1Xr1D+2zbHIq63wTY1e1t06JpTgj0VCLuag4EQCyRw02yQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprMKsWRmVeSWpSXmKPExsVy+t9jAV3WEz7BBvtWGVrcWneO1aL33Ekm i/lHgKwrX9+zWfS/Wchqce7VSkaLSfcnsFi8uHeRxaJ3wVU2i7NNb9gtZpzfx2Sx9PpFJosJ 09eyWLTuPQIUm/ySzeLnrnksDgIea+atYfS43NfL5LFz1l12j5XLv7B5bFrVyeax/dsDVo/7 3ceZPPq2rGL0+LxJLoAzqoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8x N9VWycUnQNctMwfoESWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYR1jxqrz rSwFD9kr2n7UNDBeYuti5OSQEDCRuLXiBCOELSZx4d56oDgXh5DAIkaJNy8PsUM4rUwSL/9e BetgE9CUeP5xByuILSJgKtExaSkLSBGzwBMmia5r/UwgCWEBH4kvTQ1gNouAqsSqYx+YQWxe AReJny9fAzVwAK1TkJgzyQYkzCngKnF1+wKwsBBQyeJlhRMYeRcwMqxiFE0tSC4oTkrPNdIr TswtLs1L10vOz93ECI7iZ9I7GFc1WBxiFOBgVOLhnfDOO1iINbGsuDL3EKMEB7OSCO/rZJ9g Id6UxMqq1KL8+KLSnNTiQ4zJQDdNZJYSTc4HJpi8knhDYxMzI0sjM2MTc2Nj0oSVxHkPtloH CgmkJ5akZqemFqQWwWxh4uCUamBs+cymsu6U2aUs21m6Z3wPbzslW5pkaWQ3P0Mx81faX681 CtxL1fdc960P+fuW50ZFsuHxwFxzRZWIEkHjrQftqyZ/Wau+OqxGo7nWdeHjNaJfK8R2R5aH 7V0ny9dadazvyZfv7ueYzjaczDmf0j4ze+7pKn7x/b/uVv04VxxyIn3jIlWPQ1FKLMUZiYZa zEXFiQC1g3mRJgMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, sw0312.kim@samsung.com, a.hajda@samsung.com, kyungmin.park@samsung.com, robh+dt@kernel.org, galak@codeaurora.org, kgene.kim@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some phy control registers are not kept after software reset. So this patch makes the clocks containing phy control to be set after software reset. Signed-off-by: YoungJun Cho Signed-off-by: Inki Dae Signed-off-by: Kyungmin Park --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 956e5f3..2cf1f0b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) static int exynos_dsi_init(struct exynos_dsi *dsi) { - exynos_dsi_enable_clock(dsi); exynos_dsi_reset(dsi); enable_irq(dsi->irq); exynos_dsi_wait_for_reset(dsi); + exynos_dsi_enable_clock(dsi); exynos_dsi_init_link(dsi); return 0;