From patchwork Mon Apr 21 12:28:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YoungJun Cho X-Patchwork-Id: 4024151 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 15C2FBFF02 for ; Mon, 21 Apr 2014 12:28:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89405202C8 for ; Mon, 21 Apr 2014 12:28:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C043120411 for ; Mon, 21 Apr 2014 12:28:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C64226E386; Mon, 21 Apr 2014 05:28:46 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E69606E578 for ; Mon, 21 Apr 2014 05:28:45 -0700 (PDT) Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N4D00LBDRZWBTC0@mailout1.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 21 Apr 2014 21:28:44 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.41]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 83.2B.14563.CFE05535; Mon, 21 Apr 2014 21:28:44 +0900 (KST) X-AuditID: cbfee68e-b7fd86d0000038e3-12-53550efc5b42 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 3D.A3.27725.CFE05535; Mon, 21 Apr 2014 21:28:44 +0900 (KST) Received: from localhost.localdomain ([10.252.75.90]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N4D000WURZT7I00@mmp2.samsung.com>; Mon, 21 Apr 2014 21:28:43 +0900 (KST) From: YoungJun Cho To: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [RFC v2 PATCH 02/14] drm/exynos: dsi: delay setting clocks after reset Date: Mon, 21 Apr 2014 21:28:29 +0900 Message-id: <1398083321-8668-3-git-send-email-yj44.cho@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1398083321-8668-1-git-send-email-yj44.cho@samsung.com> References: <1398083321-8668-1-git-send-email-yj44.cho@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t8zTd0/fKHBBrs/aFncWneO1aL33Ekm i/lHgKwrX9+zWfS/Wchqce7VSkaLSfcnsFi8uHeRxaJ3wVU2i7NNb9gtOicuYbeYcX4fk8XS 6xeZLCZMX8ti0br3CLvFyT+9jBYzJr9ks/i5ax6Lg5DHmnlrGD0u9/UyeeycdZfdY+XyL2we sztmsnpsWtXJ5nHn2h42j+3fHrB63O8+zuTRt2UVo8fnTXIB3FFcNimpOZllqUX6dglcGfNf xBdcZ694MTutgfEEWxcjJ4eEgInEpWndTBC2mMSFe+uB4lwcQgLLGCVmbf7MCFN09OBcqMR0 Rom5j5ewQDitTBKzFj5jBaliE9CUeP5xB5gtImAq0TFpKQuIzSywiFli8R0jEFtYwF/iwpF3 YOtYBFQlTs2+BHYGr4CzRNvjd0DbOIC2KUjMmWQDEuYUcJHYPX0J2EghoJIvzTAHTeWQ+LYg G2KMgMS3yYdYIFplJTYdYIYokZQ4uOIGywRG4QWMDKsYRVMLkguKk9KLjPSKE3OLS/PS9ZLz czcxQmKxbwfjzQPWhxiTgcZNZJYSTc4HxnJeSbyhsZmRhamJqbGRuaUZacJK4ryLHiYFCQmk J5akZqemFqQWxReV5qQWH2Jk4uCUamBUO71n1eSX6eJB8SGb3nxPm5b/ouvjaq/j4m++JQfo vzi1fnlN2oysiI93Tn2aZnx20aEN5k+3L52uM/Hj2Sklp54uci3u2njQpaFU/au/QNDBk7cF Hn0wlpry288sXGfG36TXMwwX3nOOlly5Z/X9HJsG520Tk6xYXl2tWyzHaiHuv6P1865HJkos xRmJhlrMRcWJAExJ4tvbAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGKsWRmVeSWpSXmKPExsVy+t9jQd0/fKHBBie2q1ncWneO1aL33Ekm i/lHgKwrX9+zWfS/Wchqce7VSkaLSfcnsFi8uHeRxaJ3wVU2i7NNb9gtOicuYbeYcX4fk8XS 6xeZLCZMX8ti0br3CLvFyT+9jBYzJr9ks/i5ax6Lg5DHmnlrGD0u9/UyeeycdZfdY+XyL2we sztmsnpsWtXJ5nHn2h42j+3fHrB63O8+zuTRt2UVo8fnTXIB3FENjDYZqYkpqUUKqXnJ+SmZ eem2St7B8c7xpmYGhrqGlhbmSgp5ibmptkouPgG6bpk5QM8pKZQl5pQChQISi4uV9O0wTQgN cdO1gGmM0PUNCYLrMTJAAwnrGDPmv4gvuM5e8WJ2WgPjCbYuRk4OCQETiaMH50LZYhIX7q0H srk4hASmM0rMfbyEBcJpZZKYtfAZK0gVm4CmxPOPO8BsEQFTiY5JS1lAbGaBRcwSi+8YgdjC Av4SF468YwKxWQRUJU7NvgS2gVfAWaLt8TvGLkYOoG0KEnMm2YCEOQVcJHZPXwI2Ugio5Evz Z8YJjLwLGBlWMYqmFiQXFCel5xrqFSfmFpfmpesl5+duYgTH+jOpHYwrGywOMQpwMCrx8M4o CQkWYk0sK67MPcQowcGsJMIbsR4oxJuSWFmVWpQfX1Sak1p8iDEZ6KiJzFKiyfnANJRXEm9o bGJmZGlkZmxibmxMmrCSOO+BVutAIYH0xJLU7NTUgtQimC1MHJxSDYxcryKO9B9cxM4xU2Wz f6d40F/JlcIvK3cd+dIbojbrZEaAZZnPzrb7e0Wk9i9d+LzvV/uySm79m8zzzvS5Ge2d4PRA nTmma7nnq69K4Yf2iJyZ9vyBRu7qDc/a3yy4aZuoznphZ+i6I4xyu9fb3asqNSsLX3dy/tzD f4se1aQ0ad688rhxqT6rEktxRqKhFnNRcSIAynCTFzkDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, sachin.kamat@linaro.org, sw0312.kim@samsung.com, a.hajda@samsung.com, kyungmin.park@samsung.com, robh+dt@kernel.org, laurent.pinchart@ideasonboard.com, galak@codeaurora.org, kgene.kim@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some phy control registers are not kept after software reset. So this patch makes the clocks containing phy control to be set after software reset. Signed-off-by: YoungJun Cho Acked-by: Inki Dae Acked-by: Kyungmin Park --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 956e5f3..2cf1f0b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) static int exynos_dsi_init(struct exynos_dsi *dsi) { - exynos_dsi_enable_clock(dsi); exynos_dsi_reset(dsi); enable_irq(dsi->irq); exynos_dsi_wait_for_reset(dsi); + exynos_dsi_enable_clock(dsi); exynos_dsi_init_link(dsi); return 0;