| Message ID | 1400102879-3164-2-git-send-email-zajec5@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, May 14, 2014 at 5:27 PM, Rafa? Mi?ecki <zajec5@gmail.com> wrote: > What initially seemed to be a typo in fglrx (using register 0x740c > instead of 74dc) appeared to be a correct behavior. Without this > 0x740c reg operation DCE 3 doesn't work and it seems we got code for > that already in place. > Recent RE effors allowed to finally understand this magic: > WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); > > This has been tested for possible regressions on DCE3 HD3470 (RV620). > > Signed-off-by: Rafa? Mi?ecki <zajec5@gmail.com> > --- > drivers/gpu/drm/radeon/r600_hdmi.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c > index b8b2efa..d4c13a0 100644 > --- a/drivers/gpu/drm/radeon/r600_hdmi.c > +++ b/drivers/gpu/drm/radeon/r600_hdmi.c > @@ -332,6 +332,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod > u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; > struct hdmi_avi_infoframe frame; > uint32_t offset; > + uint32_t acr_ctl; > ssize_t err; > > if (!dig || !dig->afmt) > @@ -351,15 +352,15 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod > WREG32(HDMI0_VBI_PACKET_CONTROL + offset, > HDMI0_NULL_SEND); /* send null packets when required */ > > - WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); > - > WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, > HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ > HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ > HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ > HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ > > - WREG32(HDMI0_ACR_PACKET_CONTROL + offset, > + /* DCE 3.0 uses register that's normally for CRC_CONTROL */ > + acr_ctl = ASIC_IS_DCE3(rdev) ? 0x740c : HDMI0_ACR_PACKET_CONTROL; The register offsets for these registers seems to be swapped. On DCE3, they should be: #define HDMI0_AUDIO_CRC_CONTROL 0x74dc #define HDMI0_ACR_PACKET_CONTROL 0x740c > + WREG32(acr_ctl + offset, > HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ > HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ > > -- > 1.8.4.5 >
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index b8b2efa..d4c13a0 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -332,6 +332,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; struct hdmi_avi_infoframe frame; uint32_t offset; + uint32_t acr_ctl; ssize_t err; if (!dig || !dig->afmt) @@ -351,15 +352,15 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod WREG32(HDMI0_VBI_PACKET_CONTROL + offset, HDMI0_NULL_SEND); /* send null packets when required */ - WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); - WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ - WREG32(HDMI0_ACR_PACKET_CONTROL + offset, + /* DCE 3.0 uses register that's normally for CRC_CONTROL */ + acr_ctl = ASIC_IS_DCE3(rdev) ? 0x740c : HDMI0_ACR_PACKET_CONTROL; + WREG32(acr_ctl + offset, HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
What initially seemed to be a typo in fglrx (using register 0x740c instead of 74dc) appeared to be a correct behavior. Without this 0x740c reg operation DCE 3 doesn't work and it seems we got code for that already in place. Recent RE effors allowed to finally understand this magic: WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); This has been tested for possible regressions on DCE3 HD3470 (RV620). Signed-off-by: Rafa? Mi?ecki <zajec5@gmail.com> --- drivers/gpu/drm/radeon/r600_hdmi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)