From patchwork Fri May 23 03:32:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?St=C3=A9phane_Marchesin?= X-Patchwork-Id: 4233971 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 02133BF90B for ; Fri, 23 May 2014 15:52:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3B460203AA for ; Fri, 23 May 2014 15:52:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5A3C52016C for ; Fri, 23 May 2014 15:52:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1AD526EE5B; Fri, 23 May 2014 08:52:56 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pa0-f53.google.com (mail-pa0-f53.google.com [209.85.220.53]) by gabe.freedesktop.org (Postfix) with ESMTP id DE0486ED5C for ; Thu, 22 May 2014 20:32:50 -0700 (PDT) Received: by mail-pa0-f53.google.com with SMTP id kp14so3409967pab.26 for ; Thu, 22 May 2014 20:32:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version:content-type :content-transfer-encoding; bh=1JzWmf2LdBt3bv0WA63gnONu2kzd1XR+zJMUwJ1yffI=; b=NhzuHvhHbOC0Itw+LatGUW2qejohg4gJ9FhLIt7tefY8gOrZ/7Go069ZcWtCDCf6pA NnrU+Y79TzdoCl1EJhlqUjOdC7pXKixxRd9RIqibxzqR+OoXtyUWe1uNygxMTWPr4fan dr7OhtnyMLjcps/Ml+dauNl2Mxi5UL4oDme6U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-type:content-transfer-encoding; bh=1JzWmf2LdBt3bv0WA63gnONu2kzd1XR+zJMUwJ1yffI=; b=aMlwIkevVgivc8vayMvlcce5CEOnFhjbBD5NONhYDgVShso2vt6vo4YcFz3JJBaPN/ w2fJyiDS7pxB5dfGbayS2Y6zOnEBAPjKLEN0Ev5DITlWqCCt0ARwvYHV/mcY/78JHZkz zulsSbfHZ900KpmGVWvCetTnIKH85u76v05Ku8q89SJsG6y5TO5KD+Cf+4KYlWUTLv0F EXpr4jv2NHmT/nRdyDHBBf5iQyuFVKvh/HbIJqJkP145ok9rVCnIR6sORAvAq8JwYp09 mzm6C7LdM9EX9jnByyVJestkCPh4HvzbdHhkWFlW1ZmZRMA1CQNzhMOuDi2XnBNOH+CX 6BJg== X-Gm-Message-State: ALoCoQnYeupKblOCBBbWPJVmyFRut22OY8EoB8H3zKYMLgooj/rXjWWx2nH/9dTCrEbW4LhLou+E X-Received: by 10.68.181.67 with SMTP id du3mr2354911pbc.96.1400815970673; Thu, 22 May 2014 20:32:50 -0700 (PDT) Received: from localhost ([2620:0:1000:1b01:82c1:6eff:fef8:b068]) by mx.google.com with ESMTPSA id qj3sm1982091pbc.91.2014.05.22.20.32.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 22 May 2014 20:32:50 -0700 (PDT) From: =?UTF-8?q?St=C3=A9phane=20Marchesin?= To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/3] drm/tegra: Remove pixel clock rounding Date: Thu, 22 May 2014 20:32:46 -0700 Message-Id: <1400815968-1084-1-git-send-email-marcheu@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 23 May 2014 08:52:37 -0700 Cc: =?UTF-8?q?St=C3=A9phane=20Marchesin?= , treding@nvidia.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by: Stéphane Marchesin --- drivers/gpu/drm/tegra/sor.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 49ef572..75b8690 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -863,19 +863,16 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output, struct tegra_sor *sor = to_sor(output); int err; - /* round to next MHz */ - pclk = DIV_ROUND_UP(pclk / 2, 1000000) * 1000000; - err = clk_set_parent(clk, sor->clk_parent); if (err < 0) { dev_err(sor->dev, "failed to set parent clock: %d\n", err); return err; } - err = clk_set_rate(sor->clk_parent, pclk); + err = clk_set_rate(sor->clk_parent, pclk / 2); if (err < 0) { dev_err(sor->dev, "failed to set base clock rate to %lu Hz\n", - pclk * 2); + pclk); return err; }