From patchwork Sat May 24 01:58:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?St=C3=A9phane_Marchesin?= X-Patchwork-Id: 4236441 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5057E9F1F4 for ; Sat, 24 May 2014 01:58:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7B4EE202C8 for ; Sat, 24 May 2014 01:58:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 930C52037A for ; Sat, 24 May 2014 01:58:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C70006EF04; Fri, 23 May 2014 18:58:44 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pa0-f43.google.com (mail-pa0-f43.google.com [209.85.220.43]) by gabe.freedesktop.org (Postfix) with ESMTP id BF63F6EF03 for ; Fri, 23 May 2014 18:58:39 -0700 (PDT) Received: by mail-pa0-f43.google.com with SMTP id hz1so4835371pad.16 for ; Fri, 23 May 2014 18:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=2lPVFQfPMVSigg8Kytw9A1XPsQ13JDgb56zxoQIMc24=; b=U1y/a+yC0kt2JJgeRbM28gmF9eYxugqaBHFF1+oUaof52Xks1eVPBF92Rv07oq6pNJ UCPuMzseILDosJfXjvUILZxCuBqVEArKg+YWKzpedigKJ2NqOLzlU+AtqKrIDMXSXxZb b95moLE8JA9ynU0j/4F+ejsWMMDhqDc/f9JTU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=2lPVFQfPMVSigg8Kytw9A1XPsQ13JDgb56zxoQIMc24=; b=cDp89d0IVNt8CtqThvbu84raRs7vX71m6kYp9aHEVSTloBZjb2fkLzy+lOIKvMO1ed GL3IUeFlEGQL0JZCniC2omTllZK8cnxZvU4GByCLUWeChj84YVBId5ugMiQkiLnFzwFB jCucn+qMiGk6wScEYF8gnhl76QXOr3vax9JUXaCweaztiawiwXmzbFZ4y+ITTjqilxqD KYB3HTrNtgss49Qz/SO+QY7Z+i0Y38Pp7v7wzD52HL6DE5knDq1FIGxgQYZx9GkW4ELu j5SmE6oMb+walsC9or6W9A+oMTMqz0DopFtizo+1ZeZugAX7Gk2htphUFqM1ipee20b3 z9pQ== X-Gm-Message-State: ALoCoQnC7vwKlxYIr6Ty7zrooaG29AASnQva2t/1kBMipfgo2EpUdwbZoMmU4I7cI13KuGhkjS+R X-Received: by 10.68.139.137 with SMTP id qy9mr10526662pbb.11.1400896719648; Fri, 23 May 2014 18:58:39 -0700 (PDT) Received: from localhost ([2620:0:1000:1b01:82c1:6eff:fef8:b068]) by mx.google.com with ESMTPSA id nh8sm6725246pbc.25.2014.05.23.18.58.38 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 23 May 2014 18:58:38 -0700 (PDT) From: =?UTF-8?q?St=C3=A9phane=20Marchesin?= To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/3] drm/tegra: Support setting the EMC clock Date: Fri, 23 May 2014 18:58:33 -0700 Message-Id: <1400896714-7092-2-git-send-email-marcheu@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1400896714-7092-1-git-send-email-marcheu@chromium.org> References: <1400896714-7092-1-git-send-email-marcheu@chromium.org> MIME-Version: 1.0 Cc: =?UTF-8?q?St=C3=A9phane=20Marchesin?= , treding@nvidia.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current code doesn't enable the EMC clock, without which the display cannot function, so let's enable this clock. We also need a bit of code to pick the right frequency for the EMC clock depending on the current video mode settings. Signed-off-by: Stéphane Marchesin --- drivers/gpu/drm/tegra/dc.c | 61 ++++++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/tegra/drm.h | 1 + 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index edb871d..f398dfb 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -325,6 +325,9 @@ static void tegra_crtc_disable(struct drm_crtc *crtc) } drm_vblank_off(drm, dc->pipe); + + if (dc->emc_clk) + clk_set_rate(dc->emc_clk, 0); } static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, @@ -640,6 +643,50 @@ unsigned int tegra_dc_format(uint32_t format) return WIN_COLOR_DEPTH_B8G8R8A8; } +static unsigned long tegra_emc_bw_to_freq_req(unsigned long bw) +{ + int bytes_per_emc_clock; + + if (of_machine_is_compatible("nvidia,tegra124")) + bytes_per_emc_clock = 16; + else + bytes_per_emc_clock = 8; + + return (bw + bytes_per_emc_clock - 1) / bytes_per_emc_clock; +} + +#define EMC_FREQ_CUTOFF_USE_130_PERCENT 100000000UL +#define EMC_FREQ_CUTOFF_USE_140_PERCENT 50000000UL + +static int tegra_dc_program_bandwidth(struct tegra_dc *dc, + struct drm_display_mode *mode, + struct tegra_dc_window *window) +{ + unsigned long bandwidth = mode->clock * window->bits_per_pixel / 8; + unsigned long freq; + struct clk *emc_master; + + if (!dc->emc_clk) + return 0; + + emc_master = clk_get_parent(dc->emc_clk); + freq = tegra_emc_bw_to_freq_req(bandwidth) * 1000; + freq = clk_round_rate(emc_master, freq); + + /* XXX: Add safety margins for DVFS */ + + if (freq < EMC_FREQ_CUTOFF_USE_140_PERCENT) + bandwidth += 4 * bandwidth / 10; + else if (freq < EMC_FREQ_CUTOFF_USE_130_PERCENT) + bandwidth += 3 * bandwidth / 10; + else + bandwidth += bandwidth / 10; + + freq = tegra_emc_bw_to_freq_req(bandwidth) * 1000; + + return clk_set_rate(dc->emc_clk, freq); +} + static int tegra_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted, @@ -691,7 +738,11 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc, if (err < 0) dev_err(dc->dev, "failed to enable root plane\n"); - return 0; + err = tegra_dc_program_bandwidth(dc, mode, &window); + if (err) + dev_err(dc->dev, "failed to program the EMC clock\n"); + + return err; } static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, @@ -1260,6 +1311,12 @@ static int tegra_dc_probe(struct platform_device *pdev) if (err < 0) return err; + dc->emc_clk = devm_clk_get(&pdev->dev, "emc"); + if (IS_ERR(dc->emc_clk)) + dc->emc_clk = NULL; + else + clk_prepare_enable(dc->emc_clk); + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); dc->regs = devm_ioremap_resource(&pdev->dev, regs); if (IS_ERR(dc->regs)) @@ -1312,6 +1369,8 @@ static int tegra_dc_remove(struct platform_device *pdev) } clk_disable_unprepare(dc->clk); + if (dc->emc_clk) + clk_disable_unprepare(dc->emc_clk); return 0; } diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 6753598..30d91c0 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -101,6 +101,7 @@ struct tegra_dc { struct clk *clk; struct reset_control *rst; + struct clk *emc_clk; void __iomem *regs; int irq;