From patchwork Mon Jul 7 14:51:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 4506481 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 79AD59F1C4 for ; Tue, 8 Jul 2014 16:13:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D5E5B202F8 for ; Tue, 8 Jul 2014 16:13:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2701E2035D for ; Tue, 8 Jul 2014 16:13:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05CE86E5B4; Tue, 8 Jul 2014 09:12:50 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.free-electrons.com (top.free-electrons.com [176.31.233.9]) by gabe.freedesktop.org (Postfix) with ESMTP id 14B636E3C7 for ; Mon, 7 Jul 2014 07:51:37 -0700 (PDT) Received: by mail.free-electrons.com (Postfix, from userid 106) id 7168A15E7; Mon, 7 Jul 2014 16:51:37 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 657347E9; Mon, 7 Jul 2014 16:51:36 +0200 (CEST) From: Boris BREZILLON To: Samuel Ortiz , Lee Jones , Thierry Reding , linux-pwm@vger.kernel.org, David Airlie , dri-devel@lists.freedesktop.org, Nicolas Ferre , Jean-Christophe Plagniol-Villard , Alexandre Belloni , Andrew Victor Subject: [PATCH v3 06/11] drm: add DT bindings documentation for atmel-hlcdc-dc driver Date: Mon, 7 Jul 2014 16:51:06 +0200 Message-Id: <1404744671-1629-7-git-send-email-boris.brezillon@free-electrons.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404744671-1629-1-git-send-email-boris.brezillon@free-electrons.com> References: <1404744671-1629-1-git-send-email-boris.brezillon@free-electrons.com> X-Mailman-Approved-At: Tue, 08 Jul 2014 09:12:18 -0700 Cc: Mark Rutland , devicetree@vger.kernel.org, Jean-Jacques Hiblot , Pawel Moll , Ian Campbell , Rob Herring , Laurent Pinchart , Bo Shen , Kumar Gala , Thomas Petazzoni X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display controller device. The HLCDC block provides a single RGB output port, and only supports LCD panels connection to LCD panels for now. The atmel,panel property link the HLCDC RGB output with the LCD panel connected on this port (note that the HLCDC RGB connector implementation makes use of the DRM panel framework). Connection to other external devices (DRM bridges) might be added later by mean of a new atmel,xxx (atmel,bridge) property. Signed-off-by: Boris BREZILLON --- .../devicetree/bindings/drm/atmel-hlcdc-dc.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt new file mode 100644 index 0000000..594bdb2 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt @@ -0,0 +1,59 @@ +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver + +The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device. +See Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt for more details. + +Required properties: + - compatible: value should be one of the following: + "atmel,hlcdc-dc" + - interrupts: the HLCDC interrupt definition + - pinctrl-names: the pin control state names. Should contain "default", + "rgb-444", "rgb-565", "rgb-666" and "rgb-888". + - pinctrl-[0-4]: should contain the pinctrl states described by pinctrl + names. + - atmel,panel: Should contain a phandle with 2 parameters. + The first cell is a phandle to a DRM panel device + The second cell encodes the RGB mode, which can take the following values: + * 0: RGB444 + * 1: RGB565 + * 2: RGB666 + * 3: RGB888 + The third cell encodes specific flags describing LCD signals configuration + (see Atmel's datasheet for a full description of these fields): + * bit 0: HSPOL: Horizontal Synchronization Pulse Polarity + * bit 1: VSPOL: Vertical Synchronization Pulse Polarity + * bit 2: VSPDLYS: Vertical Synchronization Pulse Start + * bit 3: VSPDLYE: Vertical Synchronization Pulse End + * bit 4: DISPPOL: Display Signal Polarity + * bit 7: DISPDLY: LCD Controller Display Power Signal Synchronization + * bit 12: VSPSU: LCD Controller Vertical synchronization Pulse Setup Configuration + * bit 13: VSPHO: LCD Controller Vertical synchronization Pulse Hold Configuration + * bit 16-20: GUARDTIME: LCD DISPLAY Guard Time + +Example: + + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-dc"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default", "rgb-444", "rgb-565", "rgb-666", "rgb-888"; + pinctrl-0 = <&pinctrl_lcd_base>; + pinctrl-1 = <&pinctrl_lcd_base &pinctrl_lcd_rgb444>; + pinctrl-2 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>; + pinctrl-3 = <&pinctrl_lcd_base &pinctrl_lcd_rgb666>; + pinctrl-4 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + };