From patchwork Thu Jul 10 21:54:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oded Gabbay X-Patchwork-Id: 4528401 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 42FF3BEEAA for ; Thu, 10 Jul 2014 23:33:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 671AC201D5 for ; Thu, 10 Jul 2014 23:33:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9B0FF2011D for ; Thu, 10 Jul 2014 23:33:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DF2C06E794; Thu, 10 Jul 2014 16:33:22 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-we0-f171.google.com (mail-we0-f171.google.com [74.125.82.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 715E56E01B for ; Thu, 10 Jul 2014 14:56:30 -0700 (PDT) Received: by mail-we0-f171.google.com with SMTP id q58so204882wes.2 for ; Thu, 10 Jul 2014 14:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w4vHg653R1utMJeK3THK6qR3QTm7E5TQAszq8ux2ML4=; b=MYIgqibklgU9RYcgEi5O1j293COO3M2g6Pbm9ibnlTFAcKLbNedaKa3xoM7G/hLanj Gfm2XgE78XE6dtKyGTC9RvlNkfJvOwcK2zwUZXWgJiF5L7c03+dBS7abWeycWZO89cDr N6M1mwnjMFcG/eNsoNcVis6wzcenG6hy/2WX5IHhmLLr6FfxDRYRxKOihbtFBBUiKptt kas0phpFHJaYPm4jqe57c6mcf6/k+Sxb/dv/U81VaPwz3qgRQtuEZMkhtaM8jgzB46t9 RVoeiE5HphnucF44x0NBej0JhjcvpYqHJRzJO83dudUwwoWQdNd+2xKf141w9K8j3sFd oXkQ== X-Received: by 10.194.121.6 with SMTP id lg6mr23586656wjb.116.1405029387913; Thu, 10 Jul 2014 14:56:27 -0700 (PDT) Received: from localhost.localdomain ([77.127.59.49]) by mx.google.com with ESMTPSA id pq9sm831097wjc.35.2014.07.10.14.56.25 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Jul 2014 14:56:27 -0700 (PDT) From: Oded Gabbay X-Google-Original-From: Oded Gabbay To: David Airlie , Alex Deucher , Jerome Glisse Subject: [PATCH 56/83] hsa/radeon: Queue Management integration with Memory Management Date: Fri, 11 Jul 2014 00:54:12 +0300 Message-Id: <1405029279-6894-28-git-send-email-oded.gabbay@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1405029279-6894-1-git-send-email-oded.gabbay@amd.com> References: <1405029279-6894-1-git-send-email-oded.gabbay@amd.com> X-Mailman-Approved-At: Thu, 10 Jul 2014 16:33:12 -0700 Cc: Andrew Lewycky , Ben Goz , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Goz This patch adding support for LDS aperture for user processes. Signed-off-by: Ben Goz Signed-off-by: Oded Gabbay --- drivers/gpu/hsa/radeon/kfd_device_queue_manager.c | 41 +++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c b/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c index c2d91c9..01573b1 100644 --- a/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c +++ b/drivers/gpu/hsa/radeon/kfd_device_queue_manager.c @@ -58,16 +58,50 @@ static inline unsigned int get_pipes_num_cpsch(void) return PIPE_PER_ME_CP_SCHEDULING - 1; } +static unsigned int get_sh_mem_bases_nybble_64(struct kfd_process *process, struct kfd_dev *dev) +{ + struct kfd_process_device *pdd; + uint32_t nybble; + + pdd = radeon_kfd_get_process_device_data(dev, process); + nybble = (pdd->lds_base >> 60) & 0x0E; + + return nybble; + +} + +static unsigned int get_sh_mem_bases_32(struct kfd_process *process, struct kfd_dev *dev) +{ + struct kfd_process_device *pdd; + unsigned int shared_base; + + pdd = radeon_kfd_get_process_device_data(dev, process); + shared_base = (pdd->lds_base >> 16) & 0xFF; + + return shared_base; +} + static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble); static void init_process_memory(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { + unsigned int temp; BUG_ON(!dqm || !qpd); + if (qpd->pqm->process->is_32bit_user_mode) { + temp = get_sh_mem_bases_32(qpd->pqm->process, dqm->dev); + qpd->sh_mem_bases = SHARED_BASE(temp); + } else { + temp = get_sh_mem_bases_nybble_64(qpd->pqm->process, dqm->dev); + qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); + } + qpd->sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED); qpd->sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED); - qpd->sh_mem_bases = compute_sh_mem_bases_64bit(6); qpd->sh_mem_ape1_limit = 0; qpd->sh_mem_ape1_base = 1; + + pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", + qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); } static void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd) @@ -84,6 +118,7 @@ static void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm WRITE_REG(dqm->dev, SH_MEM_APE1_BASE, qpd->sh_mem_ape1_base); WRITE_REG(dqm->dev, SH_MEM_APE1_LIMIT, qpd->sh_mem_ape1_limit); + WRITE_REG(dqm->dev, SH_MEM_BASES, qpd->sh_mem_bases); mqd->release_hqd(mqd); } @@ -128,6 +163,8 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, struct queue * set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid); qpd->vmid = *allocate_vmid; is_new_vmid = true; + + program_sh_mem_settings(dqm, qpd); } q->properties.vmid = qpd->vmid; @@ -418,7 +455,7 @@ static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) * We don't bother to support different top nybbles for LDS/Scratch and GPUVM. */ - BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE); + BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || top_address_nybble == 0); return PRIVATE_BASE(top_address_nybble << 12) | SHARED_BASE(top_address_nybble << 12); }