From patchwork Mon Jul 28 02:00:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inki Dae X-Patchwork-Id: 4631851 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7D7B7C033A for ; Mon, 28 Jul 2014 02:01:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 87DE72012B for ; Mon, 28 Jul 2014 02:01:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AECF020125 for ; Mon, 28 Jul 2014 02:01:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4DC86E299; Sun, 27 Jul 2014 19:01:14 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by gabe.freedesktop.org (Postfix) with ESMTP id 526EE6E299 for ; Sun, 27 Jul 2014 19:01:13 -0700 (PDT) Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N9E00EZYG9O65D0@mailout3.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 28 Jul 2014 11:01:00 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.113]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 70.0E.14752.BDEA5D35; Mon, 28 Jul 2014 11:00:59 +0900 (KST) X-AuditID: cbfee68f-b7fa26d0000039a0-5f-53d5aedbfa83 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id FB.D7.05196.BDEA5D35; Mon, 28 Jul 2014 11:00:59 +0900 (KST) Received: from daeinki-desktop.10.32.193.11 ([10.252.83.67]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N9E00GAEG9LZJA0@mmp2.samsung.com>; Mon, 28 Jul 2014 11:00:59 +0900 (KST) From: Inki Dae To: dri-devel@lists.freedesktop.org Subject: [PATCH v2 2/2] drm/exynos: dsi: add LPM (Low Power Mode) transfer support Date: Mon, 28 Jul 2014 11:00:57 +0900 Message-id: <1406512857-7213-3-git-send-email-inki.dae@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1406512857-7213-1-git-send-email-inki.dae@samsung.com> References: <1406512857-7213-1-git-send-email-inki.dae@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrALMWRmVeSWpSXmKPExsWyRsSkUPf2uqvBBmvvKFjcWneO1aL33Ekm iytf37NZTLo/gcVixvl9TBa3f/M5sHls//aA1eN+93Emj97md2wefVtWMXp83iQXwBrFZZOS mpNZllqkb5fAlbH14TT2ggaBisZ3tQ2My3i7GDk5JARMJKYs284CYYtJXLi3nq2LkYtDSGAp o8SOnrMsMEUP511jgkhMZ5TY+OIDK4TTzSRxuuMmI0gVm4CqxMQV99lAbBEBZYm/E1cxghQx CzQzSsxbuZgVJCEsECKxcMthsAYWoIZJG14yg9i8As4S7aeagWwOoHUKEnMm2YCEOQVcJHbs h5gvBFRy/+JrsPMkBLrZJRY+Pgs1R0Di2+RDLBC9shKbDjBDXC0pcXDFDZYJjMILGBlWMYqm FiQXFCelFxnrFSfmFpfmpesl5+duYgSG9ul/z/p3MN49YH2IMRlo3ERmKdHkfGBs5JXEGxqb GVmYmpgaG5lbmpEmrCTOe/9hUpCQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxvStOZ9fequq CCXsWJFZpDQzbUOyTZPNqdSXEy/JVgs+cDi00H1qknEC57pLV8/u2Wv+eM6sWkaRpTe0ixIu SWupX1bw+rDU7Xe99arGCzFV8i9z/F6ZKC1c/myVy7Y/24v5VW+e7n+1Vz3q8tHdO+Xn3Ptx WLBx6S1Jf1btC7dOSB/kVxVXiFViKc5INNRiLipOBACw1y1JgwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsVy+t9jQd3b664GG3yZK2lxa905VovecyeZ LK58fc9mMen+BBaLGef3MVnc/s3nwOax/dsDVo/73ceZPHqb37F59G1ZxejxeZNcAGtUA6NN RmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtAFSgpliTml QKGAxOJiJX07TBNCQ9x0LWAaI3R9Q4LgeowM0EDCGsaMrQ+nsRc0CFQ0vqttYFzG28XIySEh YCLxcN41JghbTOLCvfVsXYxcHEIC0xklNr74wArhdDNJnO64yQhSxSagKjFxxX02EFtEQFni 78RVjCBFzALNjBLzVi5mBUkIC4RILNxyGKyBBahh0oaXzCA2r4CzRPupZiCbA2idgsScSTYg YU4BF4kd+yHmCwGV3L/4mm0CI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmbGMGR80x6 B+OqBotDjAIcjEo8vBbBV4OFWBPLiitzDzFKcDArifC+bAcK8aYkVlalFuXHF5XmpBYfYjQF Omois5Rocj4wqvNK4g2NTcyMLI3MDS2MjM2VxHkPtloHCgmkJ5akZqemFqQWwfQxcXBKNTDa nX7XV/TWyPCpocqr3dMCUrKuJPsnBrCWMG+9e+LPDuf9GW2XlqbG3YmNU7+6dm/tEeY7S23N vkmoC5nFsjPPT1F+u479QbZ3/PO7xVHcP2p65mtKNATukzntY+/2y6Lqo2rQ1/jw5Uoahcxl X0oSnHSyBK9oHvCtsl4X8XtSerT264dRe5VYijMSDbWYi4oTARrRSpSyAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: a.hajda@samsung.com, treding@nvidia.com, linux-samsung-soc@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds LPM transfer support for video or command data. With this patch, Exynos MIPI DSI controller can transfer command or video data with HS or LP mode in accordance with mode_flags set by LCD Panel driver. Changelog v2: Enable High Speed clock only in case of stand by request. Signed-off-by: Inki Dae Acked-by: Kyungmin Park --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 5e78d45..1bed105 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -493,8 +493,11 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) | DSIM_ESC_PRESCALER(esc_div) | DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) - | DSIM_BYTE_CLK_SRC(0) - | DSIM_TX_REQUEST_HSCLK; + | DSIM_BYTE_CLK_SRC(0); + + if (!(dsi->mode_flags & MIPI_DSI_MODE_CMD_LPM)) + reg |= DSIM_TX_REQUEST_HSCLK; + writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); return 0; @@ -553,6 +556,18 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG); } +static void exynos_dsi_enable_hs_clock(struct exynos_dsi *dsi, + bool enable) +{ + u32 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); + + reg &= ~DSIM_TX_REQUEST_HSCLK; + if (enable) + reg |= DSIM_TX_REQUEST_HSCLK; + + writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); +} + static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) { u32 reg; @@ -705,6 +720,9 @@ static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) { u32 reg; + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_LPM) && enable) + exynos_dsi_enable_hs_clock(dsi, true); + reg = readl(dsi->reg_base + DSIM_MDRESOL_REG); if (enable) reg |= DSIM_MAIN_STAND_BY;