@@ -232,6 +232,9 @@ int mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, unsigned int channel,
break;
}
+ if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+ msg.flags = MIPI_DSI_MSG_USE_LPM;
+
return ops->transfer(dsi->host, &msg);
}
EXPORT_SYMBOL(mipi_dsi_dcs_write);
@@ -262,6 +265,9 @@ ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, unsigned int channel,
if (!ops || !ops->transfer)
return -ENOSYS;
+ if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+ msg.flags = MIPI_DSI_MSG_USE_LPM;
+
return ops->transfer(dsi->host, &msg);
}
EXPORT_SYMBOL(mipi_dsi_dcs_read);
@@ -96,6 +96,8 @@ void mipi_dsi_host_unregister(struct mipi_dsi_host *host);
#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
+/* transmit data in low power */
+#define MIPI_DSI_MODE_LPM BIT(11)
enum mipi_dsi_pixel_format {
MIPI_DSI_FMT_RGB888,
This patch adds a new flag, MIPI_DSI_MODE_LPM, to transmit data in low power. With this flag, msg.flags has MIPI_DSI_MSG_USE_LPM so that host driver of each SoC can clear or set relevant register bit for low power transmission. All host controllers shall support continuous clock behavior on the Clock Lane, and optionally may support non-continuous clock behavior. Both of them can transmit data in high speed or low power. With each clock behavior, non-continuous or continuous clock mode, host controller will transmit data in high speed by default so if peripheral want to receive data in low power, the peripheral driver should set MIPI_DSI_MODE_LPM flag. Signed-off-by: Inki Dae <inki.dae@samsung.com> --- drivers/gpu/drm/drm_mipi_dsi.c | 6 ++++++ include/drm/drm_mipi_dsi.h | 2 ++ 2 files changed, 8 insertions(+)