From patchwork Tue Aug 12 06:33:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inki Dae X-Patchwork-Id: 4710901 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 657B5C0338 for ; Tue, 12 Aug 2014 06:33:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8A23A20115 for ; Tue, 12 Aug 2014 06:33:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5F07220125 for ; Tue, 12 Aug 2014 06:33:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B5336E293; Mon, 11 Aug 2014 23:33:18 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by gabe.freedesktop.org (Postfix) with ESMTP id 7934789DFE for ; Mon, 11 Aug 2014 23:33:16 -0700 (PDT) Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NA6001HVKV9WQ60@mailout4.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 12 Aug 2014 15:33:09 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.112]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id A5.12.14752.425B9E35; Tue, 12 Aug 2014 15:33:08 +0900 (KST) X-AuditID: cbfee68f-b7fa26d0000039a0-00-53e9b524ec63 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 39.C3.04943.425B9E35; Tue, 12 Aug 2014 15:33:08 +0900 (KST) Received: from daeinki-desktop.10.32.193.11 ([10.252.83.67]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NA600B1FKV7TI20@mmp1.samsung.com>; Tue, 12 Aug 2014 15:33:08 +0900 (KST) From: Inki Dae To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/exynos: mipi-dsi: consider non-continuous clock mode Date: Tue, 12 Aug 2014 15:33:06 +0900 Message-id: <1407825186-5792-3-git-send-email-inki.dae@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1407825186-5792-1-git-send-email-inki.dae@samsung.com> References: <1407825186-5792-1-git-send-email-inki.dae@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWyRsSkQFdl68tgg/N39SxurTvHatF77iST xZWv79ksJt2fwOLA4rH92wNWj/vdx5k8+rasYgxgjuKySUnNySxLLdK3S+DKODV7HVvBIaGK j1M/MjYwLuPvYuTkkBAwkfh2fBYLhC0mceHeerYuRi4OIYGljBLfW+4ywRU1TWWESCxilHjS vYwFwulmkjgxsZEZpIpNQFVi4or7bCC2iICyxN+JqxhBbGYBL4nGy+vAVggL+Erc+7aWFcRm Aapf+bkZbAOvgLPEtdengOIcQNsUJOZMsgEJcwq4SBxcMgGsRAioZPe7o8wgeyUEvrNJbJmw CWqOgMS3yYdYIHplJTYdYIY4WlLi4IobLBMYhRcwMqxiFE0tSC4oTkovMtYrTswtLs1L10vO z93ECAzb0/+e9e9gvHvA+hBjMtC4icxSosn5wLDPK4k3NDYzsjA1MTU2Mrc0I01YSZz3/sOk ICGB9MSS1OzU1ILUovii0pzU4kOMTBycUg2MBr9eTt4f47Nv812rA0Kn9B3mf39tb9S8TOp/ 8MLQ3Z8UX5/RlmH64KyYo3dvQ+erztaKe/wTe5ZuzFjZfnpq0QzW8/c6n/zJ8uP/JJdxUDHZ 1mb2jKlqyd/O9j6NDH20wqxso5vT43NiKoul+1nfBU12ipru6dM8u1Tm0a2sIw+vutbbnn8i pMRSnJFoqMVcVJwIAEJL0iJxAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42I5/e+xgK7K1pfBBr9fqFvcWneO1aL33Ekm iytf37NZTLo/gcWBxWP7twesHve7jzN59G1ZxRjAHNXAaJORmpiSWqSQmpecn5KZl26r5B0c 7xxvamZgqGtoaWGupJCXmJtqq+TiE6DrlpkDtE9JoSwxpxQoFJBYXKykb4dpQmiIm64FTGOE rm9IEFyPkQEaSFjDmHFq9jq2gkNCFR+nfmRsYFzG38XIySEhYCLxrWkqI4QtJnHh3nq2LkYu DiGBRYwST7qXsUA43UwSJyY2MoNUsQmoSkxccZ8NxBYRUJb4O3EVWDezgJdE4+V1LCC2sICv xL1va1lBbBag+pWfm5lAbF4BZ4lrr08BxTmAtilIzJlkAxLmFHCROLhkAliJEFDJ7ndHmScw 8i5gZFjFKJpakFxQnJSea6hXnJhbXJqXrpecn7uJERwVz6R2MK5ssDjEKMDBqMTDO+Pvi2Ah 1sSy4srcQ4wSHMxKIrxRjS+DhXhTEiurUovy44tKc1KLDzGaAh01kVlKNDkfGLF5JfGGxiZm RpZG5oYWRsbmSuK8B1qtA4UE0hNLUrNTUwtSi2D6mDg4pRoYrTtlMiI2ftJjj5rKwS2R9znQ RXy37RH+nMYYlk271q7hz057qfBpm+maY3/u8p5TepQYo5FhWK669Ie854fD+js6Hx9UbNhj NCVxdiDDTXOXJQ46scpyxpn20+3tIj5sDPETnlot5sX+UkGL0WLdIw8557Vl+y017XhYJqur vW33OOF7+o4SS3FGoqEWc1FxIgBS8cXToAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: a.hajda@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds non-continuous clock mode support. Clock mode on Clock Lane is continuous clock by default. So if we want to transmit data in non-continuous clock mode to reduce power consumption, then host driver should clear DSIM_TX_REQUEST_HSCLK. For this, this patch makes the host driver set DSIM_TX_REQUEST_HSCLK only in case that dsi->mode_flags has no MIPI_DSI_CLOCK_NON_CONTINUOUS flag. Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 32 +++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 86aebd8..8c43c96 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -493,8 +493,17 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) | DSIM_ESC_PRESCALER(esc_div) | DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) - | DSIM_BYTE_CLK_SRC(0) - | DSIM_TX_REQUEST_HSCLK; + | DSIM_BYTE_CLK_SRC(0); + + /* + * Set DSIM_TX_REQUEST_HSCLK only in case of not requesting + * non-continous clock mode. So if MIPI_DSI_CLOCK_NON_CONTINUOUS, + * then host controller will turn off the HS clock between high-speed + * transmissions. + */ + if (!(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + reg |= DSIM_TX_REQUEST_HSCLK; + writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); return 0; @@ -701,10 +710,29 @@ static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); } +static void exynos_dsi_enable_hs_clock(struct exynos_dsi *dsi, + bool enable) +{ + u32 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); + + reg &= ~DSIM_TX_REQUEST_HSCLK; + if (enable) + reg |= DSIM_TX_REQUEST_HSCLK; + + writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); +} + static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) { u32 reg; + /* + * Set DSIM_TX_REQUEST_HSCLK. In case of video data, host controller + * will transmit the data in HS mode always. + */ + if (enable) + exynos_dsi_enable_hs_clock(dsi, true); + reg = readl(dsi->reg_base + DSIM_MDRESOL_REG); if (enable) reg |= DSIM_MAIN_STAND_BY;