| Message ID | 1408349495-25568-3-git-send-email-inki.dae@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/18/2014 10:11 AM, Inki Dae wrote: > This patch adds non-continuous clock mode support > > Clock mode on Clock Lane is continuous clock by default. > So if we want to transmit data in non-continuous clock mode > to reduce power consumption, then host driver should set > DSIM_CLKLANE_STOP bit. In this case, host controller turns off > HS clock between high speed transmissions. > > For this, this patch adds a new bit, DSIM_CLKLANE_STOP, and makes > the host driver set this bit only in case that dsi->mode_flags has > MIPI_DSI_CLOCK_NON_CONTINUOUS flag. > > Signed-off-by: Inki Dae <inki.dae@samsung.com> Acked-by: Andrzej Hajda <a.hajda@samsung.com> -- Regards Andrzej > --- > drivers/gpu/drm/exynos/exynos_drm_dsi.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c > index 442aa2d..2d47290 100644 > --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c > +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c > @@ -114,6 +114,8 @@ > #define DSIM_SYNC_INFORM (1 << 27) > #define DSIM_EOT_DISABLE (1 << 28) > #define DSIM_MFLUSH_VS (1 << 29) > +/* This flag is valid only for exynos3250/3472/4415/5260/5430 */ > +#define DSIM_CLKLANE_STOP (1 << 30) > > /* DSIM_ESCMODE */ > #define DSIM_TX_TRIGGER_RST (1 << 4) > @@ -262,6 +264,7 @@ struct exynos_dsi_driver_data { > unsigned int plltmr_reg; > > unsigned int has_freqband:1; > + unsigned int has_clklane_stop:1; > }; > > struct exynos_dsi { > @@ -304,6 +307,7 @@ struct exynos_dsi { > static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { > .plltmr_reg = 0x50, > .has_freqband = 1, > + .has_clklane_stop = 1, > }; > > static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { > @@ -569,6 +573,7 @@ static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) > > static int exynos_dsi_init_link(struct exynos_dsi *dsi) > { > + struct exynos_dsi_driver_data *driver_data = dsi->driver_data; > int timeout; > u32 reg; > u32 lanes_mask; > @@ -650,6 +655,20 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi) > reg |= DSIM_LANE_EN(lanes_mask); > writel(reg, dsi->reg_base + DSIM_CONFIG_REG); > > + /* > + * Use non-continuous clock mode if the periparal wants and > + * host controller supports > + * > + * In non-continous clock mode, host controller will turn off > + * the HS clock between high-speed transmissions to reduce > + * power consumption. > + */ > + if (driver_data->has_clklane_stop && > + dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { > + reg |= DSIM_CLKLANE_STOP; > + writel(reg, dsi->reg_base + DSIM_CONFIG_REG); > + } > + > /* Check clock and data lane state are stop state */ > timeout = 100; > do {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 442aa2d..2d47290 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -114,6 +114,8 @@ #define DSIM_SYNC_INFORM (1 << 27) #define DSIM_EOT_DISABLE (1 << 28) #define DSIM_MFLUSH_VS (1 << 29) +/* This flag is valid only for exynos3250/3472/4415/5260/5430 */ +#define DSIM_CLKLANE_STOP (1 << 30) /* DSIM_ESCMODE */ #define DSIM_TX_TRIGGER_RST (1 << 4) @@ -262,6 +264,7 @@ struct exynos_dsi_driver_data { unsigned int plltmr_reg; unsigned int has_freqband:1; + unsigned int has_clklane_stop:1; }; struct exynos_dsi { @@ -304,6 +307,7 @@ struct exynos_dsi { static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .plltmr_reg = 0x50, .has_freqband = 1, + .has_clklane_stop = 1, }; static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { @@ -569,6 +573,7 @@ static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) static int exynos_dsi_init_link(struct exynos_dsi *dsi) { + struct exynos_dsi_driver_data *driver_data = dsi->driver_data; int timeout; u32 reg; u32 lanes_mask; @@ -650,6 +655,20 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi) reg |= DSIM_LANE_EN(lanes_mask); writel(reg, dsi->reg_base + DSIM_CONFIG_REG); + /* + * Use non-continuous clock mode if the periparal wants and + * host controller supports + * + * In non-continous clock mode, host controller will turn off + * the HS clock between high-speed transmissions to reduce + * power consumption. + */ + if (driver_data->has_clklane_stop && + dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + reg |= DSIM_CLKLANE_STOP; + writel(reg, dsi->reg_base + DSIM_CONFIG_REG); + } + /* Check clock and data lane state are stop state */ timeout = 100; do {
This patch adds non-continuous clock mode support Clock mode on Clock Lane is continuous clock by default. So if we want to transmit data in non-continuous clock mode to reduce power consumption, then host driver should set DSIM_CLKLANE_STOP bit. In this case, host controller turns off HS clock between high speed transmissions. For this, this patch adds a new bit, DSIM_CLKLANE_STOP, and makes the host driver set this bit only in case that dsi->mode_flags has MIPI_DSI_CLOCK_NON_CONTINUOUS flag. Signed-off-by: Inki Dae <inki.dae@samsung.com> --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)