From patchwork Mon Aug 18 08:11:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inki Dae X-Patchwork-Id: 4732721 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2299A9F402 for ; Mon, 18 Aug 2014 08:11:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3E43420120 for ; Mon, 18 Aug 2014 08:11:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2E9E320123 for ; Mon, 18 Aug 2014 08:11:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7452D6E217; Mon, 18 Aug 2014 01:11:40 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by gabe.freedesktop.org (Postfix) with ESMTP id 2780589E3B for ; Mon, 18 Aug 2014 01:11:39 -0700 (PDT) Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NAH00IPYTFDGX90@mailout2.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 18 Aug 2014 17:11:38 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.113]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id D3.CC.13863.935B1F35; Mon, 18 Aug 2014 17:11:37 +0900 (KST) X-AuditID: cbfee690-b7f526d000003627-fc-53f1b539a909 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 04.A8.05196.935B1F35; Mon, 18 Aug 2014 17:11:37 +0900 (KST) Received: from daeinki-desktop.10.32.193.11 ([10.252.83.67]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NAH00301TFC8V30@mmp2.samsung.com>; Mon, 18 Aug 2014 17:11:37 +0900 (KST) From: Inki Dae To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/exynos: mipi-dsi: consider non-continuous clock mode Date: Mon, 18 Aug 2014 17:11:35 +0900 Message-id: <1408349495-25568-3-git-send-email-inki.dae@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1408349495-25568-1-git-send-email-inki.dae@samsung.com> References: <1408349495-25568-1-git-send-email-inki.dae@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNLMWRmVeSWpSXmKPExsWyRsSkUNdy68dgg127rCxurTvHatF77iST xZWv79ksJt2fwOLA4rH92wNWj/vdx5k8+rasYgxgjuKySUnNySxLLdK3S+DKuLT4IGvBepGK i/dPsTcwXhboYuTkkBAwkTj4/RU7hC0mceHeejYQW0hgKaPEtlv2XYwcYDVb3td2MXIBhacz Sry50sAK4XQzSTS+WcAI0sAmoCoxccV9sGYRAWWJvxNXgcWZBbwkGi+vYwGxhQV8Je59W8sK YrMA1S+//ACshlfABWjXZHaIZQoScybZgIQ5BVwlprw9ywRxj4vEx68boe78ziZx+0IwxBgB iW+TD7FAtMpKbDrADFEiKXFwxQ2WCYzCCxgZVjGKphYkFxQnpReZ6BUn5haX5qXrJefnbmIE Buzpf88m7GC8d8D6EGMy0LiJzFKiyfnAgM8riTc0NjOyMDUxNTYytzQjTVhJnFftUVKQkEB6 YklqdmpqQWpRfFFpTmrxIUYmDk6pBsa1TW1+G5wOlNdzXT7pvzh/sjHDZv6Fjo/1zpx0uTnT fuvmMKOHPFuEWl6buH199ufSZwu25uzn02UC/CftfHP2aLXHgS1qYteWXjU2v7y/ZN6GJrbk iaZNkvNj/G9r8k6/JflgWt1vC62yrs7/x/v0TiTN+qxzLTNVftqEWa/M7otPT7Szk7qgxFKc kWioxVxUnAgAsBvmPm4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42I5/e+xoK7l1o/BBtvnGFvcWneO1aL33Ekm iytf37NZTLo/gcWBxWP7twesHve7jzN59G1ZxRjAHNXAaJORmpiSWqSQmpecn5KZl26r5B0c 7xxvamZgqGtoaWGupJCXmJtqq+TiE6DrlpkDtE9JoSwxpxQoFJBYXKykb4dpQmiIm64FTGOE rm9IEFyPkQEaSFjDmHFp8UHWgvUiFRfvn2JvYLws0MXIwSEhYCKx5X1tFyMnkCkmceHeerYu Ri4OIYHpjBJvrjSwQjjdTBKNbxYwglSxCahKTFxxnw3EFhFQlvg7cRVYnFnAS6Lx8joWEFtY wFfi3re1rCA2C1D98ssPwGp4BVwktt2azA6xWEFiziQbkDCngKvElLdnmUBsIaCSj183sk9g 5F3AyLCKUTS1ILmgOCk910ivODG3uDQvXS85P3cTIzgmnknvYFzVYHGIUYCDUYmH1+P1h2Ah 1sSy4srcQ4wSHMxKIrzrmj4GC/GmJFZWpRblxxeV5qQWH2I0BTpqIrOUaHI+MF7zSuINjU3M jCyNzA0tjIzNlcR5D7ZaBwoJpCeWpGanphakFsH0MXFwSjUwcimUb14g5DddUE/D3Clq8b1T dwyz1aMLg9/vnLpIX0PoFKORWal23Lvis8uUH5zmvXty7oGLXYc5tjMunJQgz7zvZlbBsmIz nTAftw1BS0zjAue9WWJr51z04fqHCW8WZE8xvVQT/oxPo8PM9Ofsj8IOTbzzL6reLD+1pViI 5fd0sdmlwp/MlFiKMxINtZiLihMBNxXHP58CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: a.hajda@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds non-continuous clock mode support Clock mode on Clock Lane is continuous clock by default. So if we want to transmit data in non-continuous clock mode to reduce power consumption, then host driver should set DSIM_CLKLANE_STOP bit. In this case, host controller turns off HS clock between high speed transmissions. For this, this patch adds a new bit, DSIM_CLKLANE_STOP, and makes the host driver set this bit only in case that dsi->mode_flags has MIPI_DSI_CLOCK_NON_CONTINUOUS flag. Signed-off-by: Inki Dae Acked-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 442aa2d..2d47290 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -114,6 +114,8 @@ #define DSIM_SYNC_INFORM (1 << 27) #define DSIM_EOT_DISABLE (1 << 28) #define DSIM_MFLUSH_VS (1 << 29) +/* This flag is valid only for exynos3250/3472/4415/5260/5430 */ +#define DSIM_CLKLANE_STOP (1 << 30) /* DSIM_ESCMODE */ #define DSIM_TX_TRIGGER_RST (1 << 4) @@ -262,6 +264,7 @@ struct exynos_dsi_driver_data { unsigned int plltmr_reg; unsigned int has_freqband:1; + unsigned int has_clklane_stop:1; }; struct exynos_dsi { @@ -304,6 +307,7 @@ struct exynos_dsi { static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .plltmr_reg = 0x50, .has_freqband = 1, + .has_clklane_stop = 1, }; static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { @@ -569,6 +573,7 @@ static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) static int exynos_dsi_init_link(struct exynos_dsi *dsi) { + struct exynos_dsi_driver_data *driver_data = dsi->driver_data; int timeout; u32 reg; u32 lanes_mask; @@ -650,6 +655,20 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi) reg |= DSIM_LANE_EN(lanes_mask); writel(reg, dsi->reg_base + DSIM_CONFIG_REG); + /* + * Use non-continuous clock mode if the periparal wants and + * host controller supports + * + * In non-continous clock mode, host controller will turn off + * the HS clock between high-speed transmissions to reduce + * power consumption. + */ + if (driver_data->has_clklane_stop && + dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { + reg |= DSIM_CLKLANE_STOP; + writel(reg, dsi->reg_base + DSIM_CONFIG_REG); + } + /* Check clock and data lane state are stop state */ timeout = 100; do {