From patchwork Fri Sep 19 19:53:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 4939841 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CBF1C9F2EC for ; Fri, 19 Sep 2014 19:56:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CDDC2201F5 for ; Fri, 19 Sep 2014 19:56:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8E60B2010B for ; Fri, 19 Sep 2014 19:56:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 08A476E1FA; Fri, 19 Sep 2014 12:56:02 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-yk0-f170.google.com (mail-yk0-f170.google.com [209.85.160.170]) by gabe.freedesktop.org (Postfix) with ESMTP id 33BA86E1FA for ; Fri, 19 Sep 2014 12:56:00 -0700 (PDT) Received: by mail-yk0-f170.google.com with SMTP id q9so202333ykb.15 for ; Fri, 19 Sep 2014 12:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=RwKJgBJLgtJxhewMqnwliFW76L9ujA4DBRnIMr5jdkY=; b=RGkaOu6myRORQ3xDaqfJupTZt+8+KpyWDBOsmSI1oHjQfnWZCFh8DYOcHRX1pBWGpI wnofCC7SVsffaeWlp64ibJjwbI1fnRH/OYsc6p4KcE83lJgAFJIVc34Uo96H/tOkH9+W 5R2ZUXYuq20ePDOf5owPKAJ6MspeDdk4l/o+I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=RwKJgBJLgtJxhewMqnwliFW76L9ujA4DBRnIMr5jdkY=; b=eyEdTMDp1JwQ7l9GJGrNLpt0GyB1Vk7Qd4SFYC7EsffEG4SrTlu0w5KsX7nw6VMg0E ZghCrVRnSn7HZXTukwPi5182z5NogK+9GDLZkZoI4Zik/u2XWzEBjBc2EAEfCpbgrkbf BEr6o2BoX1DBOOAFDcJJXNMMC9JITDQeaNK+ECWb4xk7/eBer0QkndKZn82ioaGKiJXz ubwDE61hDXCCJcGuA7/t1OUmB62Z/ag4N8uwI4CZq52bSo5MlMLNsT+fbtXZE4mC6LJ6 rH4kjgMsJSUOinoOrM0p9zTVKyqn4VHruxyAjtATy5trnik6Pb0Es0CdEAIH+6EfY3wP S9BA== X-Gm-Message-State: ALoCoQmplWXj+qDBH96uXTqokpUmVBYSoLKHXsUFN0CzGa3hpMWLhTBKUM/ViOdGaZJPTwMqaWJf X-Received: by 10.236.119.193 with SMTP id n41mr2661187yhh.127.1411156559346; Fri, 19 Sep 2014 12:55:59 -0700 (PDT) Received: from localhost.localdomain (cpe-173-095-180-236.nc.res.rr.com. [173.95.180.236]) by mx.google.com with ESMTPSA id t6sm1182610yhg.44.2014.09.19.12.55.57 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 19 Sep 2014 12:55:58 -0700 (PDT) From: Sean Paul To: thierry.reding@gmail.com Subject: [PATCH 1/2] drm/tegra: Set the dsi lp clk parent and rate Date: Fri, 19 Sep 2014 15:53:48 -0400 Message-Id: <1411156429-19797-1-git-send-email-seanpaul@chromium.org> X-Mailer: git-send-email 2.0.0 Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Per NVidia, this clock rate should be around 70MHz in order to properly sample reads on data lane 0. In order to achieve this rate, we need to reparent the clock from clk_m which can only achieve 12MHz. Add parent_lp to the dts bindings and set the parent & rate on init. Signed-off-by: Sean Paul --- .../devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | 10 ++++++++-- drivers/gpu/drm/tegra/dsi.c | 18 ++++++++++++++++++ drivers/gpu/drm/tegra/dsi.h | 3 +++ 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index b48f4ef..fef2918 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt @@ -191,6 +191,10 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - clock-names: Can include the following entries: + - lp_parent: The parent clock for lp + - clocks: Must contain an entry for each optional entry in clock-names. + See ../clocks/clock-bindings.txt for details. - sor: serial output resource @@ -360,8 +364,10 @@ Example: compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_DSI>, - <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; - clock-names = "dsi", "parent"; + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dsi", "lp", "parent", "lp_parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index f787445..c0258ae 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -837,6 +837,7 @@ static int tegra_dsi_probe(struct platform_device *pdev) struct tegra_dsi *dsi; struct resource *regs; int err; + struct clk *lp_parent; dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); if (!dsi) @@ -879,6 +880,23 @@ static int tegra_dsi_probe(struct platform_device *pdev) return PTR_ERR(dsi->clk_lp); } + lp_parent = devm_clk_get(&pdev->dev, "lp_parent"); + if (!IS_ERR(lp_parent)) { + err = clk_set_parent(dsi->clk_lp, lp_parent); + if (err < 0) { + dev_err(&pdev->dev, "cannot set lp clock parent\n"); + return err; + } + } else { + dev_info(&pdev->dev, "no lp clock parent, using hw default\n"); + } + + err = clk_set_rate(dsi->clk_lp, DSI_LP_CLK_RATE); + if (err < 0) { + dev_err(&pdev->dev, "cannot set low-power clock rate\n"); + return err; + } + err = clk_prepare_enable(dsi->clk_lp); if (err < 0) { dev_err(&pdev->dev, "cannot enable low-power clock\n"); diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h index 5ce610d..a332caf 100644 --- a/drivers/gpu/drm/tegra/dsi.h +++ b/drivers/gpu/drm/tegra/dsi.h @@ -127,4 +127,7 @@ enum tegra_dsi_format { TEGRA_DSI_FORMAT_24P, }; +/* default lp clock rate */ +#define DSI_LP_CLK_RATE (70 * 1000 * 1000) + #endif