From patchwork Wed Oct 1 06:19:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YoungJun Cho X-Patchwork-Id: 5015521 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 885CD9F348 for ; Thu, 2 Oct 2014 03:59:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9CC152026F for ; Thu, 2 Oct 2014 03:59:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B4A732026D for ; Thu, 2 Oct 2014 03:59:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B68066EDCF; Wed, 1 Oct 2014 20:57:41 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E0656E2C0 for ; Tue, 30 Sep 2014 23:19:20 -0700 (PDT) Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NCR0035T5K6AOE0@mailout2.samsung.com> for dri-devel@lists.freedesktop.org; Wed, 01 Oct 2014 15:19:18 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.46]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 2D.2B.18484.5EC9B245; Wed, 01 Oct 2014 15:19:17 +0900 (KST) X-AuditID: cbfee68f-f791c6d000004834-04-542b9ce5e604 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 27.C1.09430.5EC9B245; Wed, 01 Oct 2014 15:19:17 +0900 (KST) Received: from localhost.localdomain ([10.252.75.90]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NCR002UR5K1JBD0@mmp2.samsung.com>; Wed, 01 Oct 2014 15:19:17 +0900 (KST) From: YoungJun Cho To: airlied@linux.ie, dri-devel@lists.freedesktop.org Subject: [PATCH 3/7] drm/exynos: fimd: modify vclk calculation for I80 i/f Date: Wed, 01 Oct 2014 15:19:09 +0900 Message-id: <1412144353-13114-4-git-send-email-yj44.cho@samsung.com> X-Mailer: git-send-email 1.9.0 In-reply-to: <1412144353-13114-1-git-send-email-yj44.cho@samsung.com> References: <1412144353-13114-1-git-send-email-yj44.cho@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrILMWRmVeSWpSXmKPExsVy+t8zPd2nc7RDDD50y1ncWneO1aL33Ekm iytf37NZTLo/gcXixb2LLBZnm96wW8yY/JLNgd1j+7cHrB73u48zefRtWcUYwBzFZZOSmpNZ llqkb5fAlbF86n3WgjkiFUsatzI1MG4X6GLk5JAQMJE4sfc/I4QtJnHh3nq2LkYuDiGBZYwS vQ/uM8IUHV29lwkiMZ1RYuesBlYIp5VJ4sHW82wgVWwCmhLPP+5gBbFFBEwlOiYtZQGxmQWq JRZPnMsEYgsLeEk82vuCHcRmEVCVOPH7Klg9r4CLxIv++WwQ2+QkpvxeAFbDKeAqMfXsKeYu Rg6gZS4S02cqQpT0s0t8nesFMUZA4tvkQywgJRICshKbDjBDlEhKHFxxg2UCo/ACRoZVjKKp BckFxUnpRcZ6xYm5xaV56XrJ+bmbGCEh3b+D8e4B60OMAhyMSjy8CgnaIUKsiWXFlbmHGE2B NkxklhJNzgdGTl5JvKGxmZGFqYmpsZG5pZmSOO9CqZ/BQgLpiSWp2ampBalF8UWlOanFhxiZ ODilGhh3ZSx9+Inh6Hm5mnedAuv+bgt0LCxOeMATIy4idCA5aE5GSY/yr0n77abGGs7/8/9i 6T2bZdvPPTv88itPWW6QW92iLedLQm/PviZhuP+zXmL2eZEorh/veIV/9iuvKZVjkVXet9Gd Qbt87VyHv/Ps886nP0zdsF/3v92c7W++xlneMGn7mnpXiaU4I9FQi7moOBEA+gM0F2QCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDIsWRmVeSWpSXmKPExsVy+t9jQd2nc7RDDHYclbK4te4cq0XvuZNM Fle+vmezmHR/AovFi3sXWSzONr1ht5gx+SWbA7vH9m8PWD3udx9n8ujbsooxgDmqgdEmIzUx JbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB2i9kkJZYk4pUCgg sbhYSd8O04TQEDddC5jGCF3fkCC4HiMDNJCwjjFj+dT7rAVzRCqWNG5lamDcLtDFyMkhIWAi cXT1XiYIW0ziwr31bF2MXBxCAtMZJXbOamCFcFqZJB5sPc8GUsUmoCnx/OMOVhBbRMBUomPS UhYQm1mgWmLxxLlgk4QFvCQe7X3BDmKzCKhKnPh9FayeV8BF4kX/fDaIbXISU34vAKvhFHCV mHr2FHMXIwfQMheJ6TMVJzDyLmBkWMUomlqQXFCclJ5rpFecmFtcmpeul5yfu4kRHDPPpHcw rmqwOMQowMGoxMNbkaQdIsSaWFZcmXuIUYKDWUmEd2IFUIg3JbGyKrUoP76oNCe1+BCjKdBR E5mlRJPzgfGcVxJvaGxiZmRpZGZsYm5srCTOe7DVOlBIID2xJDU7NbUgtQimj4mDU6qBMWGW 38ftCY1lGnFmN7sm/ZpdanDs+Y9Vyjy5Jz55izM/irsbsVz6zu7Tmncne8ZcXptaN+lld22K 5g9N25KWDVvu397xfHVAG+vOHzNnLtxe3/olU+F67NMPGyzTt2qWph1dtlsj4rmMZtzszXM1 qrfmz/df8v352WyvVedtTJOZOF8wtRwLW6DEUpyRaKjFXFScCABoJRymrwIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: a.hajda@samsung.com, kyungmin.park@samsung.com, sw0312.kim@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The I80 interface uses SYS_WE and SYS_CS to process 1 pixel data, so it requires the twice faster clock than the pixel clock. And the frame done interrupt should occurr prior to the next TE signal, H/W guy recommends to use as 1.73 times faster clock frequency. Signed-off-by: YoungJun Cho Acked-by: Inki Dae Acked-by: Kyungmin Park --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index b2f6007..05c2a97a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -81,6 +81,11 @@ #define LCD_WR_HOLD(x) ((x) << 4) #define I80IFEN_ENABLE (1 << 0) +/* I80 interface clock */ +#define I80_DATA_SAMPLING_CYCLE 2 +#define I80_TE_PERIOD_US 1667 +#define I80_DATA_TRANSACTION_TIME_US 964 + /* FIMD has totally five hardware windows. */ #define WINDOWS_NR 5 @@ -303,16 +308,25 @@ static void fimd_mgr_remove(struct exynos_drm_manager *mgr) static u32 fimd_calc_clkdiv(struct fimd_context *ctx, const struct drm_display_mode *mode) { - unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; + unsigned long ideal_clk; u32 clkdiv; if (ctx->i80_if) { /* - * The frame done interrupt should be occurred prior to the - * next TE signal. + * The I80 interface uses SYS_WE and SYS_CS to process 1 pixel + * data, so it requires the twice faster clock than the pixel + * clock[I80_DATA_SAMPLING_CYCLE]. + * And the frame done interrupt should occurr prior to the next + * TE signal, H/W guy recommends to use as 1.73 times faster + * frequency[I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US]. */ - ideal_clk *= 2; - } + ideal_clk = mode->hdisplay * mode->vdisplay * + I80_DATA_SAMPLING_CYCLE * + I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US; + } else + ideal_clk = mode->htotal * mode->vtotal; + + ideal_clk *= mode->vrefresh; /* Find the clock divider value that gets us closest to ideal_clk */ clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); @@ -431,7 +445,7 @@ static void fimd_commit(struct exynos_drm_manager *mgr) val |= VIDCON0_CLKSEL_LCD; clkdiv = fimd_calc_clkdiv(ctx, mode); - if (clkdiv > 1) + if (clkdiv >= 1) val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; writel(val, ctx->regs + VIDCON0);