From patchwork Wed Feb 25 12:46:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 5879661 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1A4669F269 for ; Wed, 25 Feb 2015 12:46:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3B22D20376 for ; Wed, 25 Feb 2015 12:46:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 66F412034F for ; Wed, 25 Feb 2015 12:46:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCAEA6E643; Wed, 25 Feb 2015 04:46:04 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F0D86E63C; Wed, 25 Feb 2015 04:46:02 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 25 Feb 2015 04:39:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,644,1418112000"; d="scan'208";a="683188266" Received: from jnikula-mobl.fi.intel.com (HELO localhost) ([10.237.72.77]) by fmsmga002.fm.intel.com with ESMTP; 25 Feb 2015 04:45:37 -0800 From: Jani Nikula To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/4] drm/dp: indentation and ordering cleanups Date: Wed, 25 Feb 2015 14:46:51 +0200 Message-Id: <1424868414-23532-1-git-send-email-jani.nikula@intel.com> X-Mailer: git-send-email 2.1.4 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Keep the DPCD macros ordered by address, and make indentation conform to the rest of the file. commit e045d20bef41707dbba676e58624b54f9f39e172 Author: Sonika Jindal Date: Thu Feb 19 13:16:44 2015 +0530 drm: Adding edp1.4 specific dpcd macros Signed-off-by: Jani Nikula Reviewed-by: Sonika Jindal --- Daniel, this might be squashed into the above commit in the drm-misc tree. --- include/drm/drm_dp_helper.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index d4803224028f..98fefe45d158 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -92,9 +92,6 @@ # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ # define DP_OUI_SUPPORT (1 << 7) -#define DP_SUPPORTED_LINK_RATES 0x010 /*eDP 1.4*/ -#define DP_MAX_SUPPORTED_RATES 0x8 - #define DP_I2C_SPEED_CAP 0x00c /* DPI */ # define DP_I2C_SPEED_1K 0x01 # define DP_I2C_SPEED_5K 0x02 @@ -105,8 +102,12 @@ #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ + #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ +# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ + /* Multiple stream transport */ #define DP_FAUX_CAP 0x020 /* 1.2 */ # define DP_FAUX_CAP_1 (1 << 0) @@ -225,7 +226,7 @@ # define DP_UP_REQ_EN (1 << 1) # define DP_UPSTREAM_IS_SRC (1 << 2) -#define DP_LINK_RATE_SET 0x115 +#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ # define DP_PSR_ENABLE (1 << 0) @@ -338,7 +339,7 @@ # define DP_SET_POWER_D3 0x2 # define DP_SET_POWER_MASK 0x3 -#define DP_EDP_DPCD_REV 0x700 +#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */