diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
index eb11ec8..021631c 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c
@@ -317,7 +317,7 @@ static void tv_setup_filter(struct drm_encoder *encoder)
 {
 	struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 	struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
-	struct drm_display_mode *mode = encoder->crtc->mode;
+	const struct drm_display_mode *mode = encoder->crtc->mode;
 	uint32_t (*filters[])[4][7] = {&tv_enc->state.hfilter,
 				       &tv_enc->state.vfilter};
 	int i, j, k;
@@ -546,7 +546,7 @@ void nv17_ctv_update_rescaler(struct drm_encoder *encoder)
 	struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 	int head = nouveau_crtc(encoder->crtc)->index;
 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
-	struct drm_display_mode *crtc_mode = encoder->crtc->mode;
+	const struct drm_display_mode *crtc_mode = encoder->crtc->mode;
 	struct drm_display_mode *output_mode =
 		&get_tv_norm(encoder)->ctv_enc_mode.mode;
 	int overscan, hmargin, vmargin, hratio, vratio;
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index b1da742..7a60ada 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -722,7 +722,7 @@ static int
 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 {
 	struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
-	struct drm_display_mode *omode, *umode = nv_crtc->base.mode;
+	const struct drm_display_mode *omode, *umode = nv_crtc->base.mode;
 	struct drm_crtc *crtc = &nv_crtc->base;
 	struct nouveau_connector *nv_connector;
 	int mode = DRM_MODE_SCALE_NONE;
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index b3ea6ae..0e36e86 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -282,7 +282,7 @@ static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 {
 	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 	struct drm_plane *plane = omap_crtc->plane;
-	struct drm_display_mode *mode = crtc->mode;
+	const struct drm_display_mode *mode = crtc->mode;
 
 	return omap_plane_mode_set(plane, crtc, crtc->primary->fb,
 			0, 0, mode->hdisplay, mode->vdisplay,
@@ -315,7 +315,7 @@ static void page_flip_worker(struct work_struct *work)
 	struct omap_crtc *omap_crtc =
 			container_of(work, struct omap_crtc, page_flip_work);
 	struct drm_crtc *crtc = &omap_crtc->base;
-	struct drm_display_mode *mode = crtc->mode;
+	const struct drm_display_mode *mode = crtc->mode;
 	struct drm_gem_object *bo;
 
 	drm_modeset_lock(&crtc->mutex, NULL);
diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c
index 83180e4..47d1a57 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -742,7 +742,7 @@ static void qxl_write_monitors_config_for_encoder(struct qxl_device *qdev,
 	int i;
 	struct qxl_output *output = drm_encoder_to_qxl_output(encoder);
 	struct qxl_head *head;
-	struct drm_display_mode *mode;
+	const struct drm_display_mode *mode;
 
 	BUG_ON(!encoder);
 	/* TODO: ugly, do better */
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index bb604f0..0b30839 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -8881,7 +8881,7 @@ void dce8_program_fmt(struct drm_encoder *encoder)
  */
 static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
 				   struct radeon_crtc *radeon_crtc,
-				   struct drm_display_mode *mode)
+				   const struct drm_display_mode *mode)
 {
 	u32 tmp, buffer_alloc, i;
 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
@@ -9325,7 +9325,7 @@ static void dce8_program_watermarks(struct radeon_device *rdev,
 				    struct radeon_crtc *radeon_crtc,
 				    u32 lb_size, u32 num_heads)
 {
-	struct drm_display_mode *mode = radeon_crtc->base.mode;
+	const struct drm_display_mode *mode = radeon_crtc->base.mode;
 	struct dce8_wm_params wm_low, wm_high;
 	u32 pixel_period;
 	u32 line_time = 0;
@@ -9453,7 +9453,7 @@ static void dce8_program_watermarks(struct radeon_device *rdev,
  */
 void dce8_bandwidth_update(struct radeon_device *rdev)
 {
-	struct drm_display_mode *mode = NULL;
+	const struct drm_display_mode *mode = NULL;
 	u32 num_heads = 0, lb_size;
 	int i;
 
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 439a0ee..acd175b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1843,8 +1843,8 @@ void evergreen_hpd_fini(struct radeon_device *rdev)
 
 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 					struct radeon_crtc *radeon_crtc,
-					struct drm_display_mode *mode,
-					struct drm_display_mode *other_mode)
+					const struct drm_display_mode *mode,
+					const struct drm_display_mode *other_mode)
 {
 	u32 tmp, buffer_alloc, i;
 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
@@ -2180,7 +2180,7 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
 					 struct radeon_crtc *radeon_crtc,
 					 u32 lb_size, u32 num_heads)
 {
-	struct drm_display_mode *mode = radeon_crtc->base.mode;
+	const struct drm_display_mode *mode = radeon_crtc->base.mode;
 	struct evergreen_wm_params wm_low, wm_high;
 	u32 dram_channels;
 	u32 pixel_period;
@@ -2341,8 +2341,8 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
  */
 void evergreen_bandwidth_update(struct radeon_device *rdev)
 {
-	struct drm_display_mode *mode0 = NULL;
-	struct drm_display_mode *mode1 = NULL;
+	const struct drm_display_mode *mode0 = NULL;
+	const struct drm_display_mode *mode1 = NULL;
 	u32 num_heads = 0, lb_size;
 	int i;
 
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 31fc514..c4a5d65 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3212,8 +3212,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
 	int critical_point = 0, critical_point2;
 /* 	uint32_t read_return_rate, time_disp1_drop_priority; */
 	int stop_req, max_stop_req;
-	struct drm_display_mode *mode1 = NULL;
-	struct drm_display_mode *mode2 = NULL;
+	const struct drm_display_mode *mode1 = NULL;
+	const struct drm_display_mode *mode2 = NULL;
 	uint32_t pixel_bytes1 = 0;
 	uint32_t pixel_bytes2 = 0;
 
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 72bdd3b..e3295c0 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -267,8 +267,8 @@ uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs690_bandwidth_update(struct radeon_device *rdev);
 void rs690_line_buffer_adjust(struct radeon_device *rdev,
-					struct drm_display_mode *mode1,
-					struct drm_display_mode *mode2);
+					const struct drm_display_mode *mode1,
+					const struct drm_display_mode *mode2);
 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
 
 /*
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 15c9085..2c3108f 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -883,8 +883,8 @@ static void rs600_mc_init(struct radeon_device *rdev)
 
 void rs600_bandwidth_update(struct radeon_device *rdev)
 {
-	struct drm_display_mode *mode0 = NULL;
-	struct drm_display_mode *mode1 = NULL;
+	const struct drm_display_mode *mode0 = NULL;
+	const struct drm_display_mode *mode1 = NULL;
 	u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
 	/* FIXME: implement full support */
 
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 0a8ce19..5bebf94 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -202,8 +202,8 @@ static void rs690_mc_init(struct radeon_device *rdev)
 }
 
 void rs690_line_buffer_adjust(struct radeon_device *rdev,
-			      struct drm_display_mode *mode1,
-			      struct drm_display_mode *mode2)
+			      const struct drm_display_mode *mode1,
+			      const struct drm_display_mode *mode2)
 {
 	u32 tmp;
 
@@ -263,7 +263,7 @@ static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 					 struct rs690_watermark *wm,
 					 bool low)
 {
-	struct drm_display_mode *mode = crtc->base.mode;
+	const struct drm_display_mode *mode = crtc->base.mode;
 	fixed20_12 a, b, c;
 	fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 	fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
@@ -449,8 +449,8 @@ static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 static void rs690_compute_mode_priority(struct radeon_device *rdev,
 					struct rs690_watermark *wm0,
 					struct rs690_watermark *wm1,
-					struct drm_display_mode *mode0,
-					struct drm_display_mode *mode1,
+					const struct drm_display_mode *mode0,
+					const struct drm_display_mode *mode1,
 					u32 *d1mode_priority_a_cnt,
 					u32 *d2mode_priority_a_cnt)
 {
@@ -572,8 +572,8 @@ static void rs690_compute_mode_priority(struct radeon_device *rdev,
 
 void rs690_bandwidth_update(struct radeon_device *rdev)
 {
-	struct drm_display_mode *mode0 = NULL;
-	struct drm_display_mode *mode1 = NULL;
+	const struct drm_display_mode *mode0 = NULL;
+	const struct drm_display_mode *mode1 = NULL;
 	struct rs690_watermark wm0_high, wm0_low;
 	struct rs690_watermark wm1_high, wm1_low;
 	u32 tmp;
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 23da03f..86e0be8 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -955,7 +955,7 @@ static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 					 struct rv515_watermark *wm,
 					 bool low)
 {
-	struct drm_display_mode *mode = crtc->base.mode;
+	const struct drm_display_mode *mode = crtc->base.mode;
 	fixed20_12 a, b, c;
 	fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 	fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
@@ -1109,8 +1109,8 @@ static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 static void rv515_compute_mode_priority(struct radeon_device *rdev,
 					struct rv515_watermark *wm0,
 					struct rv515_watermark *wm1,
-					struct drm_display_mode *mode0,
-					struct drm_display_mode *mode1,
+					const struct drm_display_mode *mode0,
+					const struct drm_display_mode *mode1,
 					u32 *d1mode_priority_a_cnt,
 					u32 *d2mode_priority_a_cnt)
 {
@@ -1232,8 +1232,8 @@ static void rv515_compute_mode_priority(struct radeon_device *rdev,
 
 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
 {
-	struct drm_display_mode *mode0 = NULL;
-	struct drm_display_mode *mode1 = NULL;
+	const struct drm_display_mode *mode0 = NULL;
+	const struct drm_display_mode *mode1 = NULL;
 	struct rv515_watermark wm0_high, wm0_low;
 	struct rv515_watermark wm1_high, wm1_low;
 	u32 tmp;
@@ -1274,8 +1274,8 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
 void rv515_bandwidth_update(struct radeon_device *rdev)
 {
 	uint32_t tmp;
-	struct drm_display_mode *mode0 = NULL;
-	struct drm_display_mode *mode1 = NULL;
+	const struct drm_display_mode *mode0 = NULL;
+	const struct drm_display_mode *mode1 = NULL;
 
 	if (!rdev->mode_info.mode_config_initialized)
 		return;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 6c7ac2b..da0480c 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1880,8 +1880,8 @@ out:
 /* watermark setup */
 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
 				   struct radeon_crtc *radeon_crtc,
-				   struct drm_display_mode *mode,
-				   struct drm_display_mode *other_mode)
+				   const struct drm_display_mode *mode,
+				   const struct drm_display_mode *other_mode)
 {
 	u32 tmp, buffer_alloc, i;
 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
@@ -2222,7 +2222,7 @@ static void dce6_program_watermarks(struct radeon_device *rdev,
 					 struct radeon_crtc *radeon_crtc,
 					 u32 lb_size, u32 num_heads)
 {
-	struct drm_display_mode *mode = radeon_crtc->base.mode;
+	const struct drm_display_mode *mode = radeon_crtc->base.mode;
 	struct dce6_wm_params wm_low, wm_high;
 	u32 dram_channels;
 	u32 pixel_period;
@@ -2380,8 +2380,8 @@ static void dce6_program_watermarks(struct radeon_device *rdev,
 
 void dce6_bandwidth_update(struct radeon_device *rdev)
 {
-	struct drm_display_mode *mode0 = NULL;
-	struct drm_display_mode *mode1 = NULL;
+	const struct drm_display_mode *mode0 = NULL;
+	const struct drm_display_mode *mode1 = NULL;
 	u32 num_heads = 0, lb_size;
 	int i;
 
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 7e91b8f..7683527 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -446,7 +446,7 @@ struct drm_crtc {
 	bool enabled;
 
 	/* Requested mode from modesetting. */
-	struct drm_display_mode *mode;
+	const struct drm_display_mode *mode;
 
 	/* Programmed mode in hw, after adjustments for encoders,
 	 * crtc, panel scaling etc. Needed for timestamping etc.
