| Message ID | 1434096538-1810-2-git-send-email-oded.gabbay@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 12, 2015 at 4:08 AM, Oded Gabbay <oded.gabbay@gmail.com> wrote: > From: Ben Goz <ben.goz@amd.com> > > Signed-off-by: Ben Goz <ben.goz@amd.com> > Acked-by: Oded Gabbay <oded.gabbay@amd.com> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Does this depend on some other patch? I'm getting a build failure: drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c: In function ‘gmc_v7_0_init_compute_vmid’: drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: error: ‘MTYPE_NONCACHED’ undeclared (first use in this function) sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; ^ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: note: each undeclared identifier is reported only once for each function it appears in Alex > --- > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 42 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 47 ++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 28 ++++++++++++++++++++ > 3 files changed, 117 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index cb790744..2c188fb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -2010,6 +2010,46 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev, > } > > /** > + * gmc_v7_0_init_compute_vmid - gart enable > + * > + * @rdev: amdgpu_device pointer > + * > + * Initialize compute vmid sh_mem registers > + * > + */ > +#define DEFAULT_SH_MEM_BASES (0x6000) > +#define FIRST_COMPUTE_VMID (8) > +#define LAST_COMPUTE_VMID (16) > +static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) > +{ > + int i; > + uint32_t sh_mem_config; > + uint32_t sh_mem_bases; > + > + /* > + * Configure apertures: > + * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) > + * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) > + * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) > + */ > + sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); > + sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << > + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; > + sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; > + mutex_lock(&adev->srbm_mutex); > + for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { > + cik_srbm_select(adev, 0, 0, 0, i); > + /* CP and shaders */ > + WREG32(mmSH_MEM_CONFIG, sh_mem_config); > + WREG32(mmSH_MEM_APE1_BASE, 1); > + WREG32(mmSH_MEM_APE1_LIMIT, 0); > + WREG32(mmSH_MEM_BASES, sh_mem_bases); > + } > + cik_srbm_select(adev, 0, 0, 0, 0); > + mutex_unlock(&adev->srbm_mutex); > +} > + > +/** > * gfx_v7_0_gpu_init - setup the 3D engine > * > * @adev: amdgpu_device pointer > @@ -2230,6 +2270,8 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) > cik_srbm_select(adev, 0, 0, 0, 0); > mutex_unlock(&adev->srbm_mutex); > > + gmc_v7_0_init_compute_vmid(adev); > + > WREG32(mmSX_DEBUG_1, 0x20); > > WREG32(mmTA_CNTL_AUX, 0x00010000); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 14242bd..e4aeb74 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -1894,6 +1894,51 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, > mutex_unlock(&adev->grbm_idx_mutex); > } > > +/** > + * gmc_v8_0_init_compute_vmid - gart enable > + * > + * @rdev: amdgpu_device pointer > + * > + * Initialize compute vmid sh_mem registers > + * > + */ > +#define DEFAULT_SH_MEM_BASES (0x6000) > +#define FIRST_COMPUTE_VMID (8) > +#define LAST_COMPUTE_VMID (16) > +static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev) > +{ > + int i; > + uint32_t sh_mem_config; > + uint32_t sh_mem_bases; > + > + /* > + * Configure apertures: > + * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) > + * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) > + * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) > + */ > + sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); > + > + sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << > + SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | > + SH_MEM_ALIGNMENT_MODE_UNALIGNED << > + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | > + MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | > + SH_MEM_CONFIG__PRIVATE_ATC_MASK; > + > + mutex_lock(&adev->srbm_mutex); > + for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { > + vi_srbm_select(adev, 0, 0, 0, i); > + /* CP and shaders */ > + WREG32(mmSH_MEM_CONFIG, sh_mem_config); > + WREG32(mmSH_MEM_APE1_BASE, 1); > + WREG32(mmSH_MEM_APE1_LIMIT, 0); > + WREG32(mmSH_MEM_BASES, sh_mem_bases); > + } > + vi_srbm_select(adev, 0, 0, 0, 0); > + mutex_unlock(&adev->srbm_mutex); > +} > + > static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > { > u32 gb_addr_config; > @@ -2113,6 +2158,8 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > vi_srbm_select(adev, 0, 0, 0, 0); > mutex_unlock(&adev->srbm_mutex); > > + gmc_v8_0_init_compute_vmid(adev); > + > mutex_lock(&adev->grbm_idx_mutex); > /* > * making sure that the following register writes will be broadcasted > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > index e3c1fde..7bb37b9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > @@ -439,6 +439,31 @@ static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) > } > > /** > + * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch > + * > + * @adev: amdgpu_device pointer > + * @enable: enable/disable the DMA MEs context switch. > + * > + * Halt or unhalt the async dma engines context switch (VI). > + */ > +static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) > +{ > + u32 f32_cntl; > + int i; > + > + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { > + f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); > + if (enable) > + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, > + AUTO_CTXSW_ENABLE, 1); > + else > + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, > + AUTO_CTXSW_ENABLE, 0); > + WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); > + } > +} > + > +/** > * sdma_v3_0_enable - stop the async dma engines > * > * @adev: amdgpu_device pointer > @@ -648,6 +673,8 @@ static int sdma_v3_0_start(struct amdgpu_device *adev) > > /* unhalt the MEs */ > sdma_v3_0_enable(adev, true); > + /* enable sdma ring preemption */ > + sdma_v3_0_ctx_switch_enable(adev, true); > > /* start the gfx rings and rlc compute queues */ > r = sdma_v3_0_gfx_resume(adev); > @@ -1079,6 +1106,7 @@ static int sdma_v3_0_hw_fini(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > + sdma_v3_0_ctx_switch_enable(adev, false); > sdma_v3_0_enable(adev, false); > > return 0; > -- > 2.4.3 >
On Wed, Jun 24, 2015 at 10:25 PM, Alex Deucher <alexdeucher@gmail.com> wrote: > On Fri, Jun 12, 2015 at 4:08 AM, Oded Gabbay <oded.gabbay@gmail.com> wrote: >> From: Ben Goz <ben.goz@amd.com> >> >> Signed-off-by: Ben Goz <ben.goz@amd.com> >> Acked-by: Oded Gabbay <oded.gabbay@amd.com> >> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > > Does this depend on some other patch? I'm getting a build failure: > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c: In function ‘gmc_v7_0_init_compute_vmid’: > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: error: > ‘MTYPE_NONCACHED’ undeclared (first use in this function) > sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; > ^ > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: note: each undeclared > identifier is reported only once for each function it appears in Strange. I just checked it while it is rebased on dave's drm-next and there is no error head of git log: 2015-06-24 - 2095197 - drm/amdgpu: Initialize compute sdma and memory from kgd <Ben Goz> 2015-06-24 - 8b72ce1 - (drm/drm-next) drm: Always enable atomic API <Daniel Stone> 2015-06-24 - fa2f97d - drm/vgem: Set unique to "vgem" <Daniel Vetter> ... Oded
On Wed, Jun 24, 2015 at 3:28 PM, Oded Gabbay <oded.gabbay@gmail.com> wrote: > On Wed, Jun 24, 2015 at 10:25 PM, Alex Deucher <alexdeucher@gmail.com> wrote: >> On Fri, Jun 12, 2015 at 4:08 AM, Oded Gabbay <oded.gabbay@gmail.com> wrote: >>> From: Ben Goz <ben.goz@amd.com> >>> >>> Signed-off-by: Ben Goz <ben.goz@amd.com> >>> Acked-by: Oded Gabbay <oded.gabbay@amd.com> >>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> >> >> Does this depend on some other patch? I'm getting a build failure: >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c: In function ‘gmc_v7_0_init_compute_vmid’: >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: error: >> ‘MTYPE_NONCACHED’ undeclared (first use in this function) >> sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; >> ^ >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: note: each undeclared >> identifier is reported only once for each function it appears in > > Strange. > I just checked it while it is rebased on dave's drm-next and there is no error > head of git log: > 2015-06-24 - 2095197 - drm/amdgpu: Initialize compute sdma and memory > from kgd <Ben Goz> > 2015-06-24 - 8b72ce1 - (drm/drm-next) drm: Always enable atomic API > <Daniel Stone> > 2015-06-24 - fa2f97d - drm/vgem: Set unique to "vgem" <Daniel Vetter> > ... You probably built with CIK support disabled. It's a kconfig option. Alex > > Oded
On Wed, Jun 24, 2015 at 10:31 PM, Alex Deucher <alexdeucher@gmail.com> wrote: > On Wed, Jun 24, 2015 at 3:28 PM, Oded Gabbay <oded.gabbay@gmail.com> wrote: >> On Wed, Jun 24, 2015 at 10:25 PM, Alex Deucher <alexdeucher@gmail.com> wrote: >>> On Fri, Jun 12, 2015 at 4:08 AM, Oded Gabbay <oded.gabbay@gmail.com> wrote: >>>> From: Ben Goz <ben.goz@amd.com> >>>> >>>> Signed-off-by: Ben Goz <ben.goz@amd.com> >>>> Acked-by: Oded Gabbay <oded.gabbay@amd.com> >>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> >>> >>> Does this depend on some other patch? I'm getting a build failure: >>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c: In function ‘gmc_v7_0_init_compute_vmid’: >>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: error: >>> ‘MTYPE_NONCACHED’ undeclared (first use in this function) >>> sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; >>> ^ >>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:2038:19: note: each undeclared >>> identifier is reported only once for each function it appears in >> >> Strange. >> I just checked it while it is rebased on dave's drm-next and there is no error >> head of git log: >> 2015-06-24 - 2095197 - drm/amdgpu: Initialize compute sdma and memory >> from kgd <Ben Goz> >> 2015-06-24 - 8b72ce1 - (drm/drm-next) drm: Always enable atomic API >> <Daniel Stone> >> 2015-06-24 - fa2f97d - drm/vgem: Set unique to "vgem" <Daniel Vetter> >> ... > > You probably built with CIK support disabled. It's a kconfig option. > > Alex > Yeah, totally forgot about it. I see the error now. I'll send a revised patch soon. Thanks Alex >> >> Oded
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index cb790744..2c188fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2010,6 +2010,46 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev, } /** + * gmc_v7_0_init_compute_vmid - gart enable + * + * @rdev: amdgpu_device pointer + * + * Initialize compute vmid sh_mem registers + * + */ +#define DEFAULT_SH_MEM_BASES (0x6000) +#define FIRST_COMPUTE_VMID (8) +#define LAST_COMPUTE_VMID (16) +static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) +{ + int i; + uint32_t sh_mem_config; + uint32_t sh_mem_bases; + + /* + * Configure apertures: + * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) + * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) + * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) + */ + sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); + sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; + sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; + mutex_lock(&adev->srbm_mutex); + for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { + cik_srbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + WREG32(mmSH_MEM_CONFIG, sh_mem_config); + WREG32(mmSH_MEM_APE1_BASE, 1); + WREG32(mmSH_MEM_APE1_LIMIT, 0); + WREG32(mmSH_MEM_BASES, sh_mem_bases); + } + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + +/** * gfx_v7_0_gpu_init - setup the 3D engine * * @adev: amdgpu_device pointer @@ -2230,6 +2270,8 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) cik_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); + gmc_v7_0_init_compute_vmid(adev); + WREG32(mmSX_DEBUG_1, 0x20); WREG32(mmTA_CNTL_AUX, 0x00010000); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 14242bd..e4aeb74 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1894,6 +1894,51 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, mutex_unlock(&adev->grbm_idx_mutex); } +/** + * gmc_v8_0_init_compute_vmid - gart enable + * + * @rdev: amdgpu_device pointer + * + * Initialize compute vmid sh_mem registers + * + */ +#define DEFAULT_SH_MEM_BASES (0x6000) +#define FIRST_COMPUTE_VMID (8) +#define LAST_COMPUTE_VMID (16) +static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev) +{ + int i; + uint32_t sh_mem_config; + uint32_t sh_mem_bases; + + /* + * Configure apertures: + * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) + * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) + * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) + */ + sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); + + sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << + SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | + SH_MEM_ALIGNMENT_MODE_UNALIGNED << + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | + MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | + SH_MEM_CONFIG__PRIVATE_ATC_MASK; + + mutex_lock(&adev->srbm_mutex); + for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { + vi_srbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + WREG32(mmSH_MEM_CONFIG, sh_mem_config); + WREG32(mmSH_MEM_APE1_BASE, 1); + WREG32(mmSH_MEM_APE1_LIMIT, 0); + WREG32(mmSH_MEM_BASES, sh_mem_bases); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) { u32 gb_addr_config; @@ -2113,6 +2158,8 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); + gmc_v8_0_init_compute_vmid(adev); + mutex_lock(&adev->grbm_idx_mutex); /* * making sure that the following register writes will be broadcasted diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index e3c1fde..7bb37b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -439,6 +439,31 @@ static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) } /** + * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs context switch. + * + * Halt or unhalt the async dma engines context switch (VI). + */ +static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) +{ + u32 f32_cntl; + int i; + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); + if (enable) + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, + AUTO_CTXSW_ENABLE, 1); + else + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, + AUTO_CTXSW_ENABLE, 0); + WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); + } +} + +/** * sdma_v3_0_enable - stop the async dma engines * * @adev: amdgpu_device pointer @@ -648,6 +673,8 @@ static int sdma_v3_0_start(struct amdgpu_device *adev) /* unhalt the MEs */ sdma_v3_0_enable(adev, true); + /* enable sdma ring preemption */ + sdma_v3_0_ctx_switch_enable(adev, true); /* start the gfx rings and rlc compute queues */ r = sdma_v3_0_gfx_resume(adev); @@ -1079,6 +1106,7 @@ static int sdma_v3_0_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + sdma_v3_0_ctx_switch_enable(adev, false); sdma_v3_0_enable(adev, false); return 0;