From patchwork Fri Jun 12 12:59:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hyungwon Hwang X-Patchwork-Id: 6598451 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8A7E5C0020 for ; Fri, 12 Jun 2015 12:59:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 40FBF20680 for ; Fri, 12 Jun 2015 12:59:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 28E6E20684 for ; Fri, 12 Jun 2015 12:59:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E0AE7A10C; Fri, 12 Jun 2015 05:59:44 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C44A6EAA9 for ; Fri, 12 Jun 2015 05:59:29 -0700 (PDT) Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NPU00F6W1F4FO20@mailout4.samsung.com> for dri-devel@lists.freedesktop.org; Fri, 12 Jun 2015 21:59:28 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.114]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id A6.48.29324.0B7DA755; Fri, 12 Jun 2015 21:59:28 +0900 (KST) X-AuditID: cbfee68d-f79106d00000728c-bc-557ad7b00033 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 45.15.05312.0B7DA755; Fri, 12 Jun 2015 21:59:28 +0900 (KST) Received: from localhost.localdomain ([10.252.82.145]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NPU002KS1F1AP00@mmp2.samsung.com>; Fri, 12 Jun 2015 21:59:27 +0900 (KST) From: Hyungwon Hwang To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v6 11/15] drm/exynos: dsi: make use of array for clock access Date: Fri, 12 Jun 2015 21:59:06 +0900 Message-id: <1434113958-15877-12-git-send-email-human.hwang@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1434113958-15877-1-git-send-email-human.hwang@samsung.com> References: <1434113958-15877-1-git-send-email-human.hwang@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRsSkSHfD9apQg+fNQhZXWqezWsw/co7V 4srX92wWS2f0sVpMuj+BxeLFvYssFjMmv2RzYPd48XUbs8f97uNMHn1bVjF6fN4kF8ASxWWT kpqTWZZapG+XwJWxdPFk5oKLyhVrdyxibmDsk+1i5OSQEDCReNR7gQ3CFpO4cG89mC0ksJRR Ys7NIpiaPX8vsncxcgHFpzNKHPnVAOX8YJRY9H0fE0gVm4CexIJrP9hBbBEBe4nFX0+xghQx C3QzSqw8/xQsISzgK/H7VhMLiM0ioCoxd8IxVhCbV8BD4uLhbSwQ6+QkTh6bDBbnBIrfPXiL BeIkd4n/9w+BbZYQ6GeXWPP7NjPEIAGJb5MPARVxACVkJTYdYIaYIylxcMUNlgmMwgsYGVYx iqYWJBcUJ6UXGeoVJ+YWl+al6yXn525iBIb36X/Pencw3j5gfYhRgINRiYc3QasqVIg1say4 MvcQoynQhonMUqLJ+cAoyiuJNzQ2M7IwNTE1NjK3NFMS51WU+hksJJCeWJKanZpakFoUX1Sa k1p8iJGJg1OqgbHXOuzb9p2+e+Zo1j0tyM3flM1k80mOdfXF0wsuM6eUbX27uOBReO7+6JjH //a2Gk5Pebw85spcidQG6ym+ax8e5l/p33JXcJn5cvdgNqUn1/4+k6g/ylYjtNc5Prfu5s2b C1PctTd+K5tRUBD485ThFwZ9bYG2B+d0alnKyuKXO515x161erUSS3FGoqEWc1FxIgA/WE3L agIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEIsWRmVeSWpSXmKPExsVy+t9jQd0N16tCDf7c4bG40jqd1WL+kXOs Fle+vmezWDqjj9Vi0v0JLBYv7l1ksZgx+SWbA7vHi6/bmD3udx9n8ujbsorR4/MmuQCWqAZG m4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygE5QUyhJz SoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGUsXT2YuuKhcsXbHIuYGxj7ZLkZO DgkBE4k9fy+yQ9hiEhfurWfrYuTiEBKYzihx5FcDO4Tzg1Fi0fd9TCBVbAJ6Eguu/QDrEBGw l1j89RQrSBGzQDejxMrzT8ESwgK+Er9vNbGA2CwCqhJzJxxjBbF5BTwkLh7exgKxTk7i5LHJ YHFOoPjdg7fA4kIC7hL/7x9in8DIu4CRYRWjaGpBckFxUnqukV5xYm5xaV66XnJ+7iZGcPw8 k97BuKrB4hCjAAejEg9vglZVqBBrYllxZe4hRgkOZiUR3u7tQCHelMTKqtSi/Pii0pzU4kOM pkBXTWSWEk3OB8Z2Xkm8obGJmZGlkbmhhZGxuZI478l8n1AhgfTEktTs1NSC1CKYPiYOTqkG RqV/NpyLbvPd0Dgq4DVDnbl4EkuH04XZ8xfrJ2+dtly15aRz7E77qGOpHpXrr5vrq7pufTaH /Wl7qcQ3idS61TwrM5NSzlb2Gp9SnpC9befq0oRp52e/OVh47Kaq7Krqgjm9h2Xj99+Ku1ab pNX6fstPx2/dlRFHDK+xXl7dzRJ8+p6mtN69bCWW4oxEQy3mouJEABIQ37G1AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: sw0312.kim@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch make the driver to use an array for clock access. The number of clocks are different from the existing MIPI DSI driver and Exynos5433 MIPI DSI driver. So this patch is needed before adding support for Exynos5433 MIPI DSI driver. Signed-off-by: Hyungwon Hwang --- Changes before: - Refer https://patchwork.kernel.org/patch/6191801 Changes for v6: - None drivers/gpu/drm/exynos/exynos_drm_dsi.c | 68 ++++++++++++++++----------------- 1 file changed, 33 insertions(+), 35 deletions(-) -- 1.9.1 diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 0b468d7..557b9d2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -211,6 +211,8 @@ REG_ADDR((dsi), (reg_idx))) #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx))) +static char *clk_names[2] = { "bus_clk", "sclk_mipi" }; + enum exynos_dsi_transfer_type { EXYNOS_DSI_TX, EXYNOS_DSI_RX, @@ -260,8 +262,7 @@ struct exynos_dsi { void __iomem *reg_base; struct phy *phy; - struct clk *sclk_clk; - struct clk *bus_clk; + struct clk **clks; struct regulator_bulk_data supplies[2]; int irq; int te_gpio; @@ -1390,7 +1391,8 @@ static const struct mipi_dsi_host_ops exynos_dsi_ops = { static int exynos_dsi_poweron(struct exynos_dsi *dsi) { - int ret; + struct exynos_dsi_driver_data *driver_data = dsi->driver_data; + int ret, i; ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); if (ret < 0) { @@ -1398,31 +1400,23 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi) return ret; } - ret = clk_prepare_enable(dsi->bus_clk); - if (ret < 0) { - dev_err(dsi->dev, "cannot enable bus clock %d\n", ret); - goto err_bus_clk; - } - - ret = clk_prepare_enable(dsi->sclk_clk); - if (ret < 0) { - dev_err(dsi->dev, "cannot enable pll clock %d\n", ret); - goto err_sclk_clk; + for (i = 0; i < driver_data->num_clks; i++) { + ret = clk_prepare_enable(dsi->clks[i]); + if (ret < 0) + goto err_clk; } ret = phy_power_on(dsi->phy); if (ret < 0) { dev_err(dsi->dev, "cannot enable phy %d\n", ret); - goto err_phy; + goto err_clk; } return 0; -err_phy: - clk_disable_unprepare(dsi->sclk_clk); -err_sclk_clk: - clk_disable_unprepare(dsi->bus_clk); -err_bus_clk: +err_clk: + while (--i > -1) + clk_disable_unprepare(dsi->clks[i]); regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); return ret; @@ -1430,7 +1424,8 @@ err_bus_clk: static void exynos_dsi_poweroff(struct exynos_dsi *dsi) { - int ret; + struct exynos_dsi_driver_data *driver_data = dsi->driver_data; + int ret, i; usleep_range(10000, 20000); @@ -1446,8 +1441,8 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi) phy_power_off(dsi->phy); - clk_disable_unprepare(dsi->sclk_clk); - clk_disable_unprepare(dsi->bus_clk); + for (i = driver_data->num_clks - 1; i > -1; i--) + clk_disable_unprepare(dsi->clks[i]); ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); if (ret < 0) @@ -1778,7 +1773,7 @@ static int exynos_dsi_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct resource *res; struct exynos_dsi *dsi; - int ret; + int ret, i; dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); if (!dsi) @@ -1813,19 +1808,22 @@ static int exynos_dsi_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi"); - if (IS_ERR(dsi->sclk_clk)) { - dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); - if (IS_ERR(dsi->sclk_clk)) { - dev_info(dev, "failed to get dsi sclk clock\n"); - eturn PTR_ERR(dsi->sclk_clk); - } - } + dsi->clks = devm_kzalloc(dev, + sizeof(*dsi->clks) * dsi->driver_data->num_clks, + GFP_KERNEL); + for (i = 0; i < dsi->driver_data->num_clks; i++) { + dsi->clks[i] = devm_clk_get(dev, clk_names[i]); + if (IS_ERR(dsi->clks[i])) { + if (strcmp(clk_names[i], "sclk_mipi") == 0) { + strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); + i--; + continue; + } - dsi->bus_clk = devm_clk_get(dev, "bus_clk"); - if (IS_ERR(dsi->bus_clk)) { - dev_info(dev, "failed to get dsi bus clock\n"); - return PTR_ERR(dsi->bus_clk); + dev_info(dev, "failed to get the clock: %s\n", + clk_names[i]); + return PTR_ERR(dsi->clks[i]); + } } res = platform_get_resource(pdev, IORESOURCE_MEM, 0);