@@ -67,7 +67,7 @@
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&ahb_gates 36>, <&ahb_gates 43>,
<&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch1_clk>;
+ <&tcon_ch1_clk>, <&dram_gates 26>;
status = "disabled";
};
@@ -76,7 +76,8 @@
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <&ahb_gates 36>, <&ahb_gates 44>,
- <&de_be_clk>, <&tcon_ch0_clk>;
+ <&de_be_clk>, <&tcon_ch0_clk>,
+ <&dram_gates 26>;
status = "disabled";
};
@@ -62,7 +62,7 @@
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch0_clk>;
+ <&tcon_ch0_clk>, <&dram_gates 26>;
status = "disabled";
};
};
@@ -53,7 +53,7 @@
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&ahb_gates 34>, <&ahb_gates 36>,
<&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch1_clk>;
+ <&tcon_ch1_clk>, <&dram_gates 26>;
status = "disabled";
};
};
@@ -338,6 +338,25 @@
clock-output-names = "usb_ohci0", "usb_phy";
};
+ dram_gates: clk@01c20100 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-dram-gates-clk";
+ reg = <0x01c20100 0x4>;
+ clocks = <&pll5 0>;
+ clock-indices = <0>,
+ <1>,
+ <25>,
+ <26>,
+ <29>,
+ <31>;
+ clock-output-names = "dram_ve",
+ "dram_csi",
+ "dram_de_fe",
+ "dram_de_be",
+ "dram_ace",
+ "dram_iep";
+ };
+
de_be_clk: clk@01c20104 {
#clock-cells = <0>;
#reset-cells = <0>;
The DRAM gates control whether the image / display devices on the SoC have access to the DRAM clock or not. Enable it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- arch/arm/boot/dts/sun5i-a10s.dtsi | 5 +++-- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- arch/arm/boot/dts/sun5i-r8.dtsi | 2 +- arch/arm/boot/dts/sun5i.dtsi | 19 +++++++++++++++++++ 4 files changed, 24 insertions(+), 4 deletions(-)