From patchwork Fri Oct 30 14:21:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 7527921 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 79EF89F40A for ; Fri, 30 Oct 2015 16:08:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9E39C207EC for ; Fri, 30 Oct 2015 16:08:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2961420822 for ; Fri, 30 Oct 2015 16:08:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 77D176ECE5; Fri, 30 Oct 2015 09:08:40 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.free-electrons.com (down.free-electrons.com [37.187.137.238]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A51E6ECBE for ; Fri, 30 Oct 2015 07:32:03 -0700 (PDT) Received: by mail.free-electrons.com (Postfix, from userid 110) id DBF8A3DEB; Fri, 30 Oct 2015 15:22:14 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-1002-69.w90-55.abo.wanadoo.fr [90.55.204.69]) by mail.free-electrons.com (Postfix) with ESMTPSA id DF6C91DB3; Fri, 30 Oct 2015 15:21:18 +0100 (CET) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , David Airlie , Thierry Reding Subject: [PATCH 17/19] ARM: sun5i: dt: Add display blocks to the DTSI Date: Fri, 30 Oct 2015 15:21:03 +0100 Message-Id: <1446214865-3972-18-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> References: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> X-Mailman-Approved-At: Fri, 30 Oct 2015 09:08:33 -0700 Cc: Thomas Petazzoni , devicetree@vger.kernel.org, Wynter Woods , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Maxime Ripard , Hans de Goede , linux-sunxi@googlegroups.com, Laurent Pinchart , Alexander Kaplan , Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The TCON and Display Engines are the two most important members of the display pipeline. With this alone, we can already use the display to an RGB interface. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 426db76c0fe6..a67f4bdf5bcc 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -481,6 +481,20 @@ #size-cells = <0>; }; + tcon: lcd-controller@01c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + status = "disabled"; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; @@ -767,5 +781,31 @@ interrupts = <82>, <83>; clocks = <&ahb_gates 28>; }; + + de: display-engine@01e00000 { + compatible = "allwinner,sun5i-a13-display-engine"; + reg = <0x01e00000 0x20000>, + <0x01e60000 0x10000>; + reg-names = "frontend0", + "backend0"; + interrupts = <47>; + interrupt-names = "engine0"; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>, <&ahb_gates 44>, + <&de_be_clk>, <&dram_gates 26>; + clock-names = "frontend0-bus", "frontend0-mod", + "frontend0-ram", "backend0-bus", + "backend0-mod", "backend0-ram"; + resets = <&de_fe_clk>, + <&de_be_clk>; + reset-names = "frontend0", + "backend0"; + + allwinner,tcon = <&tcon>; + + assigned-clocks = <&de_be_clk>; + assigned-clock-rates = <300000000>; + status = "disabled"; + }; }; };