From patchwork Fri Oct 30 14:20:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 7527981 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8C1649F37F for ; Fri, 30 Oct 2015 16:08:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 87C7720807 for ; Fri, 30 Oct 2015 16:08:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id DADA820856 for ; Fri, 30 Oct 2015 16:08:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A7B66ED00; Fri, 30 Oct 2015 09:08:49 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.free-electrons.com (down.free-electrons.com [37.187.137.238]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B3C86ECBE for ; Fri, 30 Oct 2015 07:27:03 -0700 (PDT) Received: by mail.free-electrons.com (Postfix, from userid 110) id C4351C19; Fri, 30 Oct 2015 15:21:09 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-1002-69.w90-55.abo.wanadoo.fr [90.55.204.69]) by mail.free-electrons.com (Postfix) with ESMTPSA id 83B86AFB; Fri, 30 Oct 2015 15:21:09 +0100 (CET) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , David Airlie , Thierry Reding Subject: [PATCH 01/19] clk: sunxi: Add display clock Date: Fri, 30 Oct 2015 15:20:47 +0100 Message-Id: <1446214865-3972-2-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> References: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> X-Mailman-Approved-At: Fri, 30 Oct 2015 09:08:29 -0700 Cc: Thomas Petazzoni , devicetree@vger.kernel.org, Wynter Woods , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Maxime Ripard , Hans de Goede , linux-sunxi@googlegroups.com, Laurent Pinchart , Alexander Kaplan , Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend). Add a driver for it. Signed-off-by: Maxime Ripard --- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-sun4i-display.c | 199 ++++++++++++++++++++++++++++++++++ 2 files changed, 200 insertions(+) create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index cb4c299214ce..a9e1a5885846 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -9,6 +9,7 @@ obj-y += clk-a10-mod1.o obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o obj-y += clk-mod0.o +obj-y += clk-sun4i-display.o obj-y += clk-simple-gates.o obj-y += clk-sun8i-mbus.o obj-y += clk-sun9i-core.o diff --git a/drivers/clk/sunxi/clk-sun4i-display.c b/drivers/clk/sunxi/clk-sun4i-display.c new file mode 100644 index 000000000000..f13b095c6d7a --- /dev/null +++ b/drivers/clk/sunxi/clk-sun4i-display.c @@ -0,0 +1,199 @@ +/* + * Copyright 2015 Maxime Ripard + * + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SUN4I_A10_DISPLAY_PARENTS 3 + +#define SUN4I_A10_DISPLAY_GATE_BIT 31 +#define SUN4I_A10_DISPLAY_RESET_BIT 30 +#define SUN4I_A10_DISPLAY_MUX_MASK 3 +#define SUN4I_A10_DISPLAY_MUX_SHIFT 24 +#define SUN4I_A10_DISPLAY_DIV_WIDTH 4 +#define SUN4I_A10_DISPLAY_DIV_SHIFT 0 + +struct reset_data { + void __iomem *reg; + spinlock_t *lock; + struct reset_controller_dev rcdev; +}; + +static DEFINE_SPINLOCK(sun4i_a10_display_lock); + +static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct reset_data *data = container_of(rcdev, + struct reset_data, + rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(data->lock, flags); + + reg = readl(data->reg); + writel(reg & ~BIT(SUN4I_A10_DISPLAY_RESET_BIT), data->reg); + + spin_unlock_irqrestore(data->lock, flags); + + return 0; +} + +static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct reset_data *data = container_of(rcdev, + struct reset_data, + rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(data->lock, flags); + + reg = readl(data->reg); + writel(reg | BIT(SUN4I_A10_DISPLAY_RESET_BIT), data->reg); + + spin_unlock_irqrestore(data->lock, flags); + + return 0; +} + +static int sun4i_a10_display_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct reset_data *data = container_of(rcdev, + struct reset_data, + rcdev); + + return !(readl(data->reg) & BIT(SUN4I_A10_DISPLAY_RESET_BIT)); +} + +static struct reset_control_ops sun4i_a10_display_reset_ops = { + .assert = sun4i_a10_display_assert, + .deassert = sun4i_a10_display_deassert, + .status = sun4i_a10_display_status, +}; + +static int sun4i_a10_display_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *spec) +{ + if (WARN_ON(spec->args_count != rcdev->of_reset_n_cells)) + return -EINVAL; + + /* We only have a single reset signal */ + return 0; +} + +static void __init sun4i_a10_display_setup(struct device_node *node) +{ + const char *parents[SUN4I_A10_DISPLAY_PARENTS]; + const char *clk_name = node->name; + struct reset_data *reset_data; + struct clk_divider *div; + struct clk_gate *gate; + struct clk_mux *mux; + void __iomem *reg; + struct clk *clk; + int i; + + of_property_read_string(node, "clock-output-names", &clk_name); + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", clk_name); + return; + } + + for (i = 0; i < SUN4I_A10_DISPLAY_PARENTS; i++) + parents[i] = of_clk_get_parent_name(node, i); + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return; + + mux->reg = reg; + mux->shift = SUN4I_A10_DISPLAY_MUX_SHIFT; + mux->mask = SUN4I_A10_DISPLAY_MUX_MASK; + mux->lock = &sun4i_a10_display_lock; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto free_mux; + + gate->reg = reg; + gate->bit_idx = SUN4I_A10_DISPLAY_GATE_BIT; + gate->lock = &sun4i_a10_display_lock; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto free_gate; + + div->reg = reg; + div->shift = SUN4I_A10_DISPLAY_DIV_SHIFT; + div->width = SUN4I_A10_DISPLAY_DIV_WIDTH; + div->lock = &sun4i_a10_display_lock; + + clk = clk_register_composite(NULL, clk_name, + parents, SUN4I_A10_DISPLAY_PARENTS, + &mux->hw, &clk_mux_ops, + &div->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, + 0); + if (IS_ERR(clk)) { + pr_err("%s: Couldn't register the clock\n", clk_name); + goto free_div; + } + + of_clk_add_provider(node, of_clk_src_simple_get, clk); + + reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + goto free_clk; + + reset_data->reg = reg; + reset_data->lock = &sun4i_a10_display_lock; + reset_data->rcdev.nr_resets = 1; + reset_data->rcdev.ops = &sun4i_a10_display_reset_ops; + reset_data->rcdev.of_node = node; + reset_data->rcdev.of_reset_n_cells = 0; + reset_data->rcdev.of_xlate = &sun4i_a10_display_reset_xlate; + + if (reset_controller_register(&reset_data->rcdev)) { + pr_err("%s: Couldn't register the reset controller\n", + clk_name); + goto free_reset; + } + + return; + +free_reset: + kfree(reset_data); +free_clk: + clk_unregister(clk); +free_div: + kfree(div); +free_gate: + kfree(gate); +free_mux: + kfree(mux); +} + +CLK_OF_DECLARE(sun4i_a10_display, "allwinner,sun4i-a10-display-clk", + sun4i_a10_display_setup);