From patchwork Sun Nov 22 16:09:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tobias Jakobi X-Patchwork-Id: 7676401 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E212A9F1D3 for ; Sun, 22 Nov 2015 16:10:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 016EA2065E for ; Sun, 22 Nov 2015 16:10:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0C80720674 for ; Sun, 22 Nov 2015 16:10:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 420896E2E6; Sun, 22 Nov 2015 08:10:09 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.math.uni-bielefeld.de (smtp.math.uni-bielefeld.de [129.70.45.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6524F6E2E0 for ; Sun, 22 Nov 2015 08:10:05 -0800 (PST) Received: from chidori.local (dslb-092-077-040-173.092.077.pools.vodafone-ip.de [92.77.40.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client did not present a certificate) by smtp.math.uni-bielefeld.de (Postfix) with ESMTPSA id 439F46118C; Sun, 22 Nov 2015 17:10:03 +0100 (CET) From: Tobias Jakobi To: linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 1/5] drm/exynos: mixer: refactor layer setup Date: Sun, 22 Nov 2015 17:09:40 +0100 Message-Id: <1448208584-6621-2-git-send-email-tjakobi@math.uni-bielefeld.de> X-Mailer: git-send-email 2.4.9 In-Reply-To: <1448208584-6621-1-git-send-email-tjakobi@math.uni-bielefeld.de> References: <1448208584-6621-1-git-send-email-tjakobi@math.uni-bielefeld.de> Cc: dri-devel@lists.freedesktop.org, Tobias Jakobi , gustavo.padovan@collabora.co.uk, m.szyprowski@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP First step in allowing a more generic way to setup complex blending for the different layers. Signed-off-by: Tobias Jakobi --- drivers/gpu/drm/exynos/exynos_mixer.c | 84 ++++++++++++++++++++++++++++++----- 1 file changed, 73 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 7498c6e..2c1cea3 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -63,6 +63,11 @@ struct mixer_resources { struct clk *mout_mixer; }; +struct layer_cfg { + unsigned int index; + unsigned int priority; +}; + enum mixer_version_id { MXR_VER_0_0_0_16, MXR_VER_16_0_33_0, @@ -92,6 +97,8 @@ struct mixer_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[MIXER_WIN_NR]; + const struct layer_cfg *layer_cfg; + unsigned int num_layer; int pipe; unsigned long flags; bool interlace; @@ -110,6 +117,34 @@ struct mixer_drv_data { bool has_sclk; }; +/* + * The default layer priorities for non-VP (video processor) + * and VP mixer configurations. + * + * A higher priority means that the layer is at the top of + * the layer stack. + * Configurations have to be specified with its entries + * sorted with increasing priority. + * + * The default config assumes the following usage scenario: + * layer1: OSD [top] + * layer0: main framebuffer + * video layer: video overlay [bottom] + * Note that the video layer is only usable when the + * VP is available. + */ + +static const struct layer_cfg nonvp_default_cfg[] = { + { .index = 0, .priority = 1 }, /* layer0 */ + { .index = 1, .priority = 2 }, /* layer1 */ +}; + +static const struct layer_cfg vp_default_cfg[] = { + { .index = 2, .priority = 1 }, /* video layer */ + { .index = 0, .priority = 2 }, /* layer0 */ + { .index = 1, .priority = 3 }, /* layer1 */ +}; + static const u8 filter_y_horiz_tap8[] = { 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 0, 0, @@ -268,6 +303,34 @@ static void vp_default_filter(struct mixer_resources *res) filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); } +static void mixer_layer_priority(struct mixer_context *ctx) +{ + u32 val = 0; + unsigned int i, priority; + + for (i = 0; i < ctx->num_layer; ++i) { + priority = ctx->layer_cfg[i].priority; + BUG_ON(priority > 15); + + switch (ctx->layer_cfg[i].index) { + case 0: + val |= MXR_LAYER_CFG_GRP0_VAL(priority); + break; + case 1: + val |= MXR_LAYER_CFG_GRP1_VAL(priority); + break; + case 2: + val |= MXR_LAYER_CFG_VP_VAL(priority); + break; + default: + BUG_ON(true); + break; + } + } + + mixer_reg_write(&ctx->mixer_res, MXR_LAYER_CFG, val); +} + static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable) { struct mixer_resources *res = &ctx->mixer_res; @@ -673,17 +736,7 @@ static void mixer_win_reset(struct mixer_context *ctx) mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST, MXR_STATUS_BURST_MASK); - /* setting default layer priority: layer1 > layer0 > video - * because typical usage scenario would be - * layer1 - OSD - * layer0 - framebuffer - * video - video overlay - */ - val = MXR_LAYER_CFG_GRP1_VAL(3); - val |= MXR_LAYER_CFG_GRP0_VAL(2); - if (ctx->vp_enabled) - val |= MXR_LAYER_CFG_VP_VAL(1); - mixer_reg_write(res, MXR_LAYER_CFG, val); + mixer_layer_priority(ctx); /* setting background color */ mixer_reg_write(res, MXR_BG_COLOR0, 0x008080); @@ -1209,6 +1262,15 @@ static int mixer_probe(struct platform_device *pdev) ctx->vp_enabled = drv->is_vp_enabled; ctx->has_sclk = drv->has_sclk; ctx->mxr_ver = drv->version; + + if (drv->is_vp_enabled) { + ctx->layer_cfg = vp_default_cfg; + ctx->num_layer = ARRAY_SIZE(vp_default_cfg); + } else { + ctx->layer_cfg = nonvp_default_cfg; + ctx->num_layer = ARRAY_SIZE(nonvp_default_cfg); + } + init_waitqueue_head(&ctx->wait_vsync_queue); atomic_set(&ctx->wait_vsync_event, 0);