From patchwork Thu Jan 21 02:50:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 8077051 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B61F1BEEE5 for ; Thu, 21 Jan 2016 02:51:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 08971207A4 for ; Thu, 21 Jan 2016 02:51:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 63DDF207B2 for ; Thu, 21 Jan 2016 02:50:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B50F6E1E9; Wed, 20 Jan 2016 18:50:49 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kmu-office.ch (mail.kmu-office.ch [178.209.48.109]) by gabe.freedesktop.org (Postfix) with ESMTPS id 07B95899A5 for ; Wed, 20 Jan 2016 18:50:48 -0800 (PST) Received: from trochilidae.toradex.int (75-146-58-181-Washington.hfc.comcastbusiness.net [75.146.58.181]) by mail.kmu-office.ch (Postfix) with ESMTPSA id CF7885C1527; Thu, 21 Jan 2016 03:49:36 +0100 (CET) From: Stefan Agner To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/fsl-dcu: use flat regmap cache Date: Wed, 20 Jan 2016 18:50:27 -0800 Message-Id: <1453344627-3894-2-git-send-email-stefan@agner.ch> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1453344627-3894-1-git-send-email-stefan@agner.ch> References: <1453344627-3894-1-git-send-email-stefan@agner.ch> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1453344578; bh=+ikgTaeUZymzHgU/2bJfBwPZoyTJbdJFgIutd9l9pbI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=dHLSuZixpLPuOx6tkd78rJmlLEvcl00sJfEwYaTyyGWLTuQ6KdaVMzFJwgzkODPcjL1c3ojOgPTTN5s3MfMLOp2n27bw9AQbkcVaxyLrDnhar1AO92YtbcJVcMzaUp1aPchwDFUZjDVt1seJ313kh96sO6Y5oak3JEPjWqaULJs= Cc: meng.yi@nxp.com, alison.wang@freescale.com, daniel.vetter@ffwll.ch, linux-kernel@vger.kernel.org, Mark Brown X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Using flat regmap cache instead of RB-tree to avoid the following lockdep warning on driver load: [ 0.697285] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755 lockdep_trace_alloc+0x15c/0x160() [ 0.697449] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) The RB-tree regmap cache needs to allocate new space on first writes. However, allocations in an atomic context (e.g. when a spinlock is held) are not allowed. The function regmap_write calls map->lock, which acquires a spinlock in the fast_io case. Since the FSL DCU driver uses MMIO, the regmap bus of type regmap_mmio is being used which has fast_io set to true. The MMIO space of the DCU driver is reasonable condense, hence using the much faster flat regmap cache is anyway the better choice. Signed-off-by: Stefan Agner Cc: Mark Brown --- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 20 ++++++++++++-------- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 6 ++++-- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index e01c813..971c520 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -36,11 +36,11 @@ static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg) return false; } -static const struct regmap_config fsl_dcu_regmap_config = { +static struct regmap_config fsl_dcu_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_FLAT, .volatile_reg = fsl_dcu_drm_is_volatile_reg, }; @@ -260,12 +260,14 @@ static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = { .name = "ls1021a", .total_layer = 16, .max_layer = 4, + .max_register = LS1021A_DCU_MAX_REGISTER, }; static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = { .name = "vf610", .total_layer = 64, .max_layer = 6, + .max_register = VF610_DCU_MAX_REGISTER, }; static const struct of_device_id fsl_dcu_of_match[] = { @@ -331,6 +333,14 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev) return ret; } + id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node); + if (!id) + return -ENODEV; + + drm = drm_dev_alloc(driver, dev); + fsl_dev->soc = id->data; + + fsl_dcu_regmap_config.max_register = fsl_dev->soc->max_register; fsl_dev->regmap = devm_regmap_init_mmio(dev, base, &fsl_dcu_regmap_config); if (IS_ERR(fsl_dev->regmap)) { @@ -338,12 +348,6 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev) return PTR_ERR(fsl_dev->regmap); } - id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node); - if (!id) - return -ENODEV; - fsl_dev->soc = id->data; - - drm = drm_dev_alloc(driver, dev); if (!drm) return -ENOMEM; diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h index 2a724f3..7c296a0 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h @@ -114,8 +114,6 @@ #define DCU_UPDATE_MODE_MODE BIT(31) #define DCU_UPDATE_MODE_READREG BIT(30) -#define DCU_DCFB_MAX 0x300 - #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40) #define DCU_LAYER_HEIGHT(x) ((x) << 16) @@ -155,6 +153,9 @@ #define DCU_LAYER_POST_SKIP(x) ((x) << 16) #define DCU_LAYER_PRE_SKIP(x) (x) +#define VF610_DCU_MAX_REGISTER 0x11fc +#define LS1021A_DCU_MAX_REGISTER 0x5fc + #define FSL_DCU_RGB565 4 #define FSL_DCU_RGB888 5 #define FSL_DCU_ARGB8888 6 @@ -175,6 +176,7 @@ struct fsl_dcu_soc_data { unsigned int total_layer; /*max layer number DCU supported*/ unsigned int max_layer; + unsigned int max_register; }; struct fsl_dcu_drm_device {