@@ -168,6 +168,7 @@
#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */
+#define PCI_CHIP_SKYLAKE_H_GT1 0x190B
#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */
#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
#define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */
@@ -182,6 +183,7 @@
#define PCI_CHIP_SKYLAKE_GT3 0x1926
#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */
#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A
+#define PCI_CHIP_SKYLAKE_MEDIA_SRV_GT4 0x192D
#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932
#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A
#define PCI_CHIP_SKYLAKE_H_GT4 0x193B
@@ -376,7 +378,8 @@
#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_H_GT1)
#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
(devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \
@@ -396,7 +399,8 @@
(devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
(devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \
(devid) == PCI_CHIP_SKYLAKE_H_GT4 || \
- (devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
+ (devid) == PCI_CHIP_SKYLAKE_WKS_GT4 || \
+ (devid) == PCI_CHIP_SKYLAKE_MEDIA_SRV_GT4)
#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \
(devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \
A new list yielded new devices that apparently have shipped, or will ship. Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> --- intel/intel_chipset.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)