[1/3] drm/radeon: fix indentation.

Message ID	1458129407-4940-1-git-send-email-jglisse@redhat.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <dri-devel-bounces@lists.freedesktop.org> From: jglisse@redhat.com To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/3] drm/radeon: fix indentation. Date: Wed, 16 Mar 2016 12:56:45 +0100 Message-Id: <1458129407-4940-1-git-send-email-jglisse@redhat.com> MIME-Version: 1.0 Cc: Alex Deucher <alexander.deucher@amd.com>, =?UTF-8?q?J=C3=A9rome=20Glisse?= <jglisse@redhat.com> Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>

Am 16.03.2016 um 12:56 schrieb jglisse@redhat.com: > From: Jérome Glisse <jglisse@redhat.com> > > I hate doing this but it hurts my eyes to go over code that does not > comply with indentation rules. Only thing that is not only space change > is in atom.c all other files are space indentation issues. > > Signed-off-by: Jérôme Glisse <jglisse@redhat.com> > Cc: Alex Deucher <alexander.deucher@amd.com> Oh, yes please. Patch is Acked-by: Christian König <christian.koenig@amd.com>. > --- > drivers/gpu/drm/radeon/atom.c | 7 +- > drivers/gpu/drm/radeon/atombios_crtc.c | 6 +- > drivers/gpu/drm/radeon/atombios_dp.c | 4 +- > drivers/gpu/drm/radeon/btc_dpm.c | 41 +++--- > drivers/gpu/drm/radeon/ci_dpm.c | 42 +++--- > drivers/gpu/drm/radeon/ci_smc.c | 8 +- > drivers/gpu/drm/radeon/cik.c | 6 +- > drivers/gpu/drm/radeon/cypress_dpm.c | 8 +- > drivers/gpu/drm/radeon/evergreen.c | 2 +- > drivers/gpu/drm/radeon/evergreen_cs.c | 32 ++--- > drivers/gpu/drm/radeon/evergreen_hdmi.c | 2 +- > drivers/gpu/drm/radeon/kv_dpm.c | 4 +- > drivers/gpu/drm/radeon/ni.c | 4 +- > drivers/gpu/drm/radeon/ni_dpm.c | 170 ++++++++++++------------ > drivers/gpu/drm/radeon/r600.c | 8 +- > drivers/gpu/drm/radeon/r600_cs.c | 20 +-- > drivers/gpu/drm/radeon/r600_dpm.c | 6 +- > drivers/gpu/drm/radeon/r600_hdmi.c | 4 +- > drivers/gpu/drm/radeon/radeon_atombios.c | 6 +- > drivers/gpu/drm/radeon/radeon_device.c | 8 +- > drivers/gpu/drm/radeon/radeon_display.c | 6 +- > drivers/gpu/drm/radeon/radeon_fb.c | 6 +- > drivers/gpu/drm/radeon/radeon_ib.c | 4 +- > drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 92 ++++++------- > drivers/gpu/drm/radeon/radeon_object.c | 6 +- > drivers/gpu/drm/radeon/radeon_pm.c | 2 +- > drivers/gpu/drm/radeon/radeon_semaphore.c | 4 +- > drivers/gpu/drm/radeon/radeon_uvd.c | 8 +- > drivers/gpu/drm/radeon/radeon_vce.c | 22 +-- > drivers/gpu/drm/radeon/radeon_vm.c | 19 +-- > drivers/gpu/drm/radeon/rs780_dpm.c | 2 +- > drivers/gpu/drm/radeon/rv6xx_dpm.c | 18 +-- > drivers/gpu/drm/radeon/rv740_dpm.c | 16 +-- > drivers/gpu/drm/radeon/rv770_dpm.c | 46 +++---- > drivers/gpu/drm/radeon/si.c | 44 +++--- > drivers/gpu/drm/radeon/si_dpm.c | 98 +++++++------- > drivers/gpu/drm/radeon/sumo_dpm.c | 6 +- > drivers/gpu/drm/radeon/trinity_dpm.c | 24 ++-- > drivers/gpu/drm/radeon/vce_v2_0.c | 2 +- > 39 files changed, 407 insertions(+), 406 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c > index ec1593a..f66c33d 100644 > --- a/drivers/gpu/drm/radeon/atom.c > +++ b/drivers/gpu/drm/radeon/atom.c > @@ -66,9 +66,10 @@ int atom_debug = 0; > static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); > int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); > > -static uint32_t atom_arg_mask[8] = > - { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, > -0xFF000000 }; > +static uint32_t atom_arg_mask[8] = { > + 0xFFFFFFFF, 0x0000FFFF, 0x00FFFF00, 0xFFFF0000, > + 0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000 > +}; > static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; > > static int atom_dst_to_src[8][4] = { > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c > index e187bec..cf61e08 100644 > --- a/drivers/gpu/drm/radeon/atombios_crtc.c > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c > @@ -1665,11 +1665,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, > } > > int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, > - struct drm_framebuffer *fb, > + struct drm_framebuffer *fb, > int x, int y, enum mode_set_atomic state) > { > - struct drm_device *dev = crtc->dev; > - struct radeon_device *rdev = dev->dev_private; > + struct drm_device *dev = crtc->dev; > + struct radeon_device *rdev = dev->dev_private; > > if (ASIC_IS_DCE4(rdev)) > return dce4_crtc_do_set_base(crtc, fb, x, y, 1); > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index 44ee72e..ae1ab4d 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -37,10 +37,10 @@ > #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE > > static char *voltage_names[] = { > - "0.4V", "0.6V", "0.8V", "1.2V" > + "0.4V", "0.6V", "0.8V", "1.2V" > }; > static char *pre_emph_names[] = { > - "0dB", "3.5dB", "6dB", "9.5dB" > + "0dB", "3.5dB", "6dB", "9.5dB" > }; > > /***** radeon AUX functions *****/ > diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c > index 69556f5..38e5123 100644 > --- a/drivers/gpu/drm/radeon/btc_dpm.c > +++ b/drivers/gpu/drm/radeon/btc_dpm.c > @@ -1163,12 +1163,11 @@ u32 btc_valid_sclk[40] = > 155000, 160000, 165000, 170000, 175000, 180000, 185000, 190000, 195000, 200000 > }; > > -static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = > -{ > - { 10000, 30000, RADEON_SCLK_UP }, > - { 15000, 30000, RADEON_SCLK_UP }, > - { 20000, 30000, RADEON_SCLK_UP }, > - { 25000, 30000, RADEON_SCLK_UP } > +static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = { > + { 10000, 30000, RADEON_SCLK_UP }, > + { 15000, 30000, RADEON_SCLK_UP }, > + { 20000, 30000, RADEON_SCLK_UP }, > + { 25000, 30000, RADEON_SCLK_UP } > }; > > void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, > @@ -1637,14 +1636,14 @@ static int btc_init_smc_table(struct radeon_device *rdev, > cypress_populate_smc_voltage_tables(rdev, table); > > switch (rdev->pm.int_thermal_type) { > - case THERMAL_TYPE_EVERGREEN: > - case THERMAL_TYPE_EMC2103_WITH_INTERNAL: > + case THERMAL_TYPE_EVERGREEN: > + case THERMAL_TYPE_EMC2103_WITH_INTERNAL: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; > break; > - case THERMAL_TYPE_NONE: > + case THERMAL_TYPE_NONE: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; > break; > - default: > + default: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; > break; > } > @@ -1860,37 +1859,37 @@ static bool btc_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) > case MC_SEQ_RAS_TIMING >> 2: > *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; > break; > - case MC_SEQ_CAS_TIMING >> 2: > + case MC_SEQ_CAS_TIMING >> 2: > *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; > break; > - case MC_SEQ_MISC_TIMING >> 2: > + case MC_SEQ_MISC_TIMING >> 2: > *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; > break; > - case MC_SEQ_MISC_TIMING2 >> 2: > + case MC_SEQ_MISC_TIMING2 >> 2: > *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; > break; > - case MC_SEQ_RD_CTL_D0 >> 2: > + case MC_SEQ_RD_CTL_D0 >> 2: > *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; > break; > - case MC_SEQ_RD_CTL_D1 >> 2: > + case MC_SEQ_RD_CTL_D1 >> 2: > *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; > break; > - case MC_SEQ_WR_CTL_D0 >> 2: > + case MC_SEQ_WR_CTL_D0 >> 2: > *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; > break; > - case MC_SEQ_WR_CTL_D1 >> 2: > + case MC_SEQ_WR_CTL_D1 >> 2: > *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; > break; > - case MC_PMG_CMD_EMRS >> 2: > + case MC_PMG_CMD_EMRS >> 2: > *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; > break; > - case MC_PMG_CMD_MRS >> 2: > + case MC_PMG_CMD_MRS >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; > break; > - case MC_PMG_CMD_MRS1 >> 2: > + case MC_PMG_CMD_MRS1 >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; > break; > - default: > + default: > result = false; > break; > } > diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c > index 4a09947..35e0fc3 100644 > --- a/drivers/gpu/drm/radeon/ci_dpm.c > +++ b/drivers/gpu/drm/radeon/ci_dpm.c > @@ -192,9 +192,9 @@ static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev); > > static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) > { > - struct ci_power_info *pi = rdev->pm.dpm.priv; > + struct ci_power_info *pi = rdev->pm.dpm.priv; > > - return pi; > + return pi; > } > > static struct ci_ps *ci_get_ps(struct radeon_ps *rps) > @@ -1632,7 +1632,7 @@ static int ci_notify_hw_of_power_source(struct radeon_device *rdev, > else > power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); > > - ci_set_power_limit(rdev, power_limit); > + ci_set_power_limit(rdev, power_limit); > > if (pi->caps_automatic_dc_transition) { > if (ac_power) > @@ -2017,9 +2017,9 @@ static void ci_enable_display_gap(struct radeon_device *rdev) > { > u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); > > - tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); > - tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | > - DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); > + tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); > + tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | > + DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); > > WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); > } > @@ -2938,8 +2938,8 @@ static int ci_populate_single_memory_level(struct radeon_device *rdev, > > memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); > memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); > - memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); > - memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); > + memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); > + memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); > > memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); > memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); > @@ -3152,7 +3152,7 @@ static int ci_calculate_sclk_params(struct radeon_device *rdev, > > spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; > spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); > - spll_func_cntl_3 |= SPLL_DITHEN; > + spll_func_cntl_3 |= SPLL_DITHEN; > > if (pi->caps_sclk_ss_support) { > struct radeon_atom_ss ss; > @@ -3229,7 +3229,7 @@ static int ci_populate_single_graphic_level(struct radeon_device *rdev, > graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; > > graphic_level->Flags = cpu_to_be32(graphic_level->Flags); > - graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); > + graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); > graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); > graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); > graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); > @@ -4393,7 +4393,7 @@ static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) > break; > case MC_SEQ_CAS_TIMING >> 2: > *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; > - break; > + break; > case MC_SEQ_MISC_TIMING >> 2: > *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; > break; > @@ -4625,7 +4625,7 @@ static int ci_initialize_mc_reg_table(struct radeon_device *rdev) > if (ret) > goto init_mc_done; > > - ret = ci_copy_vbios_mc_reg_table(table, ci_table); > + ret = ci_copy_vbios_mc_reg_table(table, ci_table); > if (ret) > goto init_mc_done; > > @@ -4916,7 +4916,7 @@ static int ci_set_private_data_variables_based_on_pptable(struct radeon_device * > allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; > rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = > allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; > - rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = > + rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = > allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; > > return 0; > @@ -5517,7 +5517,7 @@ static int ci_parse_power_table(struct radeon_device *rdev) > struct _NonClockInfoArray *non_clock_info_array; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > u8 *power_state_offset; > struct ci_ps *ps; > @@ -5693,8 +5693,8 @@ int ci_dpm_init(struct radeon_device *rdev) > return ret; > } > > - pi->dll_default_on = false; > - pi->sram_end = SMC_RAM_END; > + pi->dll_default_on = false; > + pi->sram_end = SMC_RAM_END; > > pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; > pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; > @@ -5734,9 +5734,9 @@ int ci_dpm_init(struct radeon_device *rdev) > pi->caps_uvd_dpm = true; > pi->caps_vce_dpm = true; > > - ci_get_leakage_voltages(rdev); > - ci_patch_dependency_tables_with_leakage(rdev); > - ci_set_private_data_variables_based_on_pptable(rdev); > + ci_get_leakage_voltages(rdev); > + ci_patch_dependency_tables_with_leakage(rdev); > + ci_set_private_data_variables_based_on_pptable(rdev); > > rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = > kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); > @@ -5839,7 +5839,7 @@ int ci_dpm_init(struct radeon_device *rdev) > pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; > else > rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; > - } > + } > > if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { > if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) > @@ -5860,7 +5860,7 @@ int ci_dpm_init(struct radeon_device *rdev) > #endif > > if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, > - &frev, &crev, &data_offset)) { > + &frev, &crev, &data_offset)) { > pi->caps_sclk_ss_support = true; > pi->caps_mclk_ss_support = true; > pi->dynamic_ss = true; > diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c > index 35c6f64..24760ee 100644 > --- a/drivers/gpu/drm/radeon/ci_smc.c > +++ b/drivers/gpu/drm/radeon/ci_smc.c > @@ -194,11 +194,11 @@ PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev) > return PPSMC_Result_OK; > > for (i = 0; i < rdev->usec_timeout; i++) { > - tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); > - if ((tmp & CKEN) == 0) > + tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); > + if ((tmp & CKEN) == 0) > break; > - udelay(1); > - } > + udelay(1); > + } > > return PPSMC_Result_OK; > } > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 0600140..f2a4c0f 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -1712,7 +1712,7 @@ static void cik_init_golden_registers(struct radeon_device *rdev) > */ > u32 cik_get_xclk(struct radeon_device *rdev) > { > - u32 reference_clock = rdev->clock.spll.reference_freq; > + u32 reference_clock = rdev->clock.spll.reference_freq; > > if (rdev->flags & RADEON_IS_IGP) { > if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) > @@ -9709,13 +9709,13 @@ uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev) > mutex_lock(&rdev->gpu_clock_mutex); > WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); > clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | > - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); > + ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); > mutex_unlock(&rdev->gpu_clock_mutex); > return clock; > } > > static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock, > - u32 cntl_reg, u32 status_reg) > + u32 cntl_reg, u32 status_reg) > { > int r, i; > struct atom_clock_dividers dividers; > diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c > index ca05858..a4edd07 100644 > --- a/drivers/gpu/drm/radeon/cypress_dpm.c > +++ b/drivers/gpu/drm/radeon/cypress_dpm.c > @@ -1620,14 +1620,14 @@ static int cypress_init_smc_table(struct radeon_device *rdev, > cypress_populate_smc_voltage_tables(rdev, table); > > switch (rdev->pm.int_thermal_type) { > - case THERMAL_TYPE_EVERGREEN: > - case THERMAL_TYPE_EMC2103_WITH_INTERNAL: > + case THERMAL_TYPE_EVERGREEN: > + case THERMAL_TYPE_EMC2103_WITH_INTERNAL: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; > break; > - case THERMAL_TYPE_NONE: > + case THERMAL_TYPE_NONE: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; > break; > - default: > + default: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; > break; > } > diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c > index 2ad4628..76c4bdf 100644 > --- a/drivers/gpu/drm/radeon/evergreen.c > +++ b/drivers/gpu/drm/radeon/evergreen.c > @@ -1140,7 +1140,7 @@ static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock, > int r, i; > struct atom_clock_dividers dividers; > > - r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > + r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > clock, false, &dividers); > if (r) > return r; > diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c > index 46f87d4..9e93205 100644 > --- a/drivers/gpu/drm/radeon/evergreen_cs.c > +++ b/drivers/gpu/drm/radeon/evergreen_cs.c > @@ -1816,8 +1816,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - (idx_value & 0xfffffff0) + > - ((u64)(tmp & 0xff) << 32); > + (idx_value & 0xfffffff0) + > + ((u64)(tmp & 0xff) << 32); > > ib[idx + 0] = offset; > ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); > @@ -1862,8 +1862,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - idx_value + > - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); > + idx_value + > + ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); > > ib[idx+0] = offset; > ib[idx+1] = upper_32_bits(offset) & 0xff; > @@ -1897,8 +1897,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - idx_value + > - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); > + idx_value + > + ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); > > ib[idx+0] = offset; > ib[idx+1] = upper_32_bits(offset) & 0xff; > @@ -1925,8 +1925,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - radeon_get_ib_value(p, idx+1) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + radeon_get_ib_value(p, idx+1) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = offset; > ib[idx+2] = upper_32_bits(offset) & 0xff; > @@ -2098,8 +2098,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); > ib[idx+2] = upper_32_bits(offset) & 0xff; > @@ -2239,8 +2239,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > return -EINVAL; > } > offset = reloc->gpu_offset + > - (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = offset & 0xfffffff8; > ib[idx+2] = upper_32_bits(offset) & 0xff; > @@ -2261,8 +2261,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = offset & 0xfffffffc; > ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); > @@ -2283,8 +2283,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = offset & 0xfffffffc; > ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); > diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c > index 3cf04a2..f766c96 100644 > --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c > +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c > @@ -206,7 +206,7 @@ void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, > * build a AVI Info Frame > */ > void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, > - unsigned char *buffer, size_t size) > + unsigned char *buffer, size_t size) > { > uint8_t *frame = buffer + 3; > > diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c > index 2d71da4..d024074 100644 > --- a/drivers/gpu/drm/radeon/kv_dpm.c > +++ b/drivers/gpu/drm/radeon/kv_dpm.c > @@ -2640,7 +2640,7 @@ static int kv_parse_power_table(struct radeon_device *rdev) > struct _NonClockInfoArray *non_clock_info_array; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > u8 *power_state_offset; > struct kv_ps *ps; > @@ -2738,7 +2738,7 @@ int kv_dpm_init(struct radeon_device *rdev) > for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) > pi->at[i] = TRINITY_AT_DFLT; > > - pi->sram_end = SMC_RAM_END; > + pi->sram_end = SMC_RAM_END; > > /* Enabling nb dpm on an asrock system prevents dpm from working */ > if (rdev->pdev->subsystem_vendor == 0x1849) > diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c > index 158872e..b88d63c9 100644 > --- a/drivers/gpu/drm/radeon/ni.c > +++ b/drivers/gpu/drm/radeon/ni.c > @@ -1257,7 +1257,7 @@ static void cayman_gpu_init(struct radeon_device *rdev) > tmp = RREG32_CG(CG_CGTT_LOCAL_0); > tmp &= ~0x00380000; > WREG32_CG(CG_CGTT_LOCAL_0, tmp); > - tmp = RREG32_CG(CG_CGTT_LOCAL_1); > + tmp = RREG32_CG(CG_CGTT_LOCAL_1); > tmp &= ~0x0e000000; > WREG32_CG(CG_CGTT_LOCAL_1, tmp); > } > @@ -2634,7 +2634,7 @@ int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) > struct atom_clock_dividers dividers; > int r, i; > > - r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > + r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > ecclk, false, &dividers); > if (r) > return r; > diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c > index c3d531a..4a601f9 100644 > --- a/drivers/gpu/drm/radeon/ni_dpm.c > +++ b/drivers/gpu/drm/radeon/ni_dpm.c > @@ -725,9 +725,9 @@ extern int ni_mc_load_microcode(struct radeon_device *rdev); > > struct ni_power_info *ni_get_pi(struct radeon_device *rdev) > { > - struct ni_power_info *pi = rdev->pm.dpm.priv; > + struct ni_power_info *pi = rdev->pm.dpm.priv; > > - return pi; > + return pi; > } > > struct ni_ps *ni_get_ps(struct radeon_ps *rps) > @@ -1096,9 +1096,9 @@ static void ni_stop_smc(struct radeon_device *rdev) > > static int ni_process_firmware_header(struct radeon_device *rdev) > { > - struct rv7xx_power_info *pi = rv770_get_pi(rdev); > - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > - struct ni_power_info *ni_pi = ni_get_pi(rdev); > + struct rv7xx_power_info *pi = rv770_get_pi(rdev); > + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > + struct ni_power_info *ni_pi = ni_get_pi(rdev); > u32 tmp; > int ret; > > @@ -1202,14 +1202,14 @@ static int ni_enter_ulp_state(struct radeon_device *rdev) > struct rv7xx_power_info *pi = rv770_get_pi(rdev); > > if (pi->gfx_clock_gating) { > - WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); > + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); > WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); > - WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); > + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); > RREG32(GB_ADDR_CONFIG); > - } > + } > > WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), > - ~HOST_SMC_MSG_MASK); > + ~HOST_SMC_MSG_MASK); > > udelay(25000); > > @@ -1321,12 +1321,12 @@ static void ni_populate_mvdd_value(struct radeon_device *rdev, > u32 mclk, > NISLANDS_SMC_VOLTAGE_VALUE *voltage) > { > - struct rv7xx_power_info *pi = rv770_get_pi(rdev); > + struct rv7xx_power_info *pi = rv770_get_pi(rdev); > struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > > if (!pi->mvdd_control) { > voltage->index = eg_pi->mvdd_high_index; > - voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); > + voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); > return; > } > > @@ -1510,47 +1510,47 @@ int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, > u32 mc_cg_config; > > switch (arb_freq_src) { > - case MC_CG_ARB_FREQ_F0: > + case MC_CG_ARB_FREQ_F0: > mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); > mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); > burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; > break; > - case MC_CG_ARB_FREQ_F1: > + case MC_CG_ARB_FREQ_F1: > mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); > mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); > burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; > break; > - case MC_CG_ARB_FREQ_F2: > + case MC_CG_ARB_FREQ_F2: > mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); > mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); > burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; > break; > - case MC_CG_ARB_FREQ_F3: > + case MC_CG_ARB_FREQ_F3: > mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); > mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); > burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; > break; > - default: > + default: > return -EINVAL; > } > > switch (arb_freq_dest) { > - case MC_CG_ARB_FREQ_F0: > + case MC_CG_ARB_FREQ_F0: > WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); > WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); > WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); > break; > - case MC_CG_ARB_FREQ_F1: > + case MC_CG_ARB_FREQ_F1: > WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); > WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); > WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); > break; > - case MC_CG_ARB_FREQ_F2: > + case MC_CG_ARB_FREQ_F2: > WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); > WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); > WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); > break; > - case MC_CG_ARB_FREQ_F3: > + case MC_CG_ARB_FREQ_F3: > WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); > WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); > WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); > @@ -1621,9 +1621,7 @@ static int ni_populate_memory_timing_parameters(struct radeon_device *rdev, > (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); > > > - radeon_atom_set_engine_dram_timings(rdev, > - pl->sclk, > - pl->mclk); > + radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk); > > dram_timing = RREG32(MC_ARB_DRAM_TIMING); > dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); > @@ -1867,9 +1865,9 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev, > > mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; > > - if (pi->mem_gddr5) > - mpll_dq_func_cntl &= ~PDNB; > - mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; > + if (pi->mem_gddr5) > + mpll_dq_func_cntl &= ~PDNB; > + mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; > > > mclk_pwrmgt_cntl |= (MRDCKA0_RESET | > @@ -1891,15 +1889,15 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev, > MRDCKD1_PDNB); > > dll_cntl |= (MRDCKA0_BYPASS | > - MRDCKA1_BYPASS | > - MRDCKB0_BYPASS | > - MRDCKB1_BYPASS | > - MRDCKC0_BYPASS | > - MRDCKC1_BYPASS | > - MRDCKD0_BYPASS | > - MRDCKD1_BYPASS); > - > - spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; > + MRDCKA1_BYPASS | > + MRDCKB0_BYPASS | > + MRDCKB1_BYPASS | > + MRDCKC0_BYPASS | > + MRDCKC1_BYPASS | > + MRDCKD0_BYPASS | > + MRDCKD1_BYPASS); > + > + spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; > spll_func_cntl_2 |= SCLK_MUX_SEL(4); > > table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); > @@ -2089,7 +2087,7 @@ static int ni_populate_sclk_value(struct radeon_device *rdev, > > static int ni_init_smc_spll_table(struct radeon_device *rdev) > { > - struct rv7xx_power_info *pi = rv770_get_pi(rdev); > + struct rv7xx_power_info *pi = rv770_get_pi(rdev); > struct ni_power_info *ni_pi = ni_get_pi(rdev); > SMC_NISLANDS_SPLL_DIV_TABLE *spll_table; > NISLANDS_SMC_SCLK_VALUE sclk_params; > @@ -2311,8 +2309,8 @@ static int ni_convert_power_level_to_smc(struct radeon_device *rdev, > NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) > { > struct rv7xx_power_info *pi = rv770_get_pi(rdev); > - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > - struct ni_power_info *ni_pi = ni_get_pi(rdev); > + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > + struct ni_power_info *ni_pi = ni_get_pi(rdev); > int ret; > bool dll_state_on; > u16 std_vddc; > @@ -2391,8 +2389,8 @@ static int ni_populate_smc_t(struct radeon_device *rdev, > struct radeon_ps *radeon_state, > NISLANDS_SMC_SWSTATE *smc_state) > { > - struct rv7xx_power_info *pi = rv770_get_pi(rdev); > - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > + struct rv7xx_power_info *pi = rv770_get_pi(rdev); > + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > struct ni_ps *state = ni_get_ps(radeon_state); > u32 a_t; > u32 t_l, t_h; > @@ -2451,8 +2449,8 @@ static int ni_populate_power_containment_values(struct radeon_device *rdev, > struct radeon_ps *radeon_state, > NISLANDS_SMC_SWSTATE *smc_state) > { > - struct rv7xx_power_info *pi = rv770_get_pi(rdev); > - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > + struct rv7xx_power_info *pi = rv770_get_pi(rdev); > + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > struct ni_power_info *ni_pi = ni_get_pi(rdev); > struct ni_ps *state = ni_get_ps(radeon_state); > u32 prev_sclk; > @@ -2595,7 +2593,7 @@ static int ni_enable_power_containment(struct radeon_device *rdev, > struct radeon_ps *radeon_new_state, > bool enable) > { > - struct ni_power_info *ni_pi = ni_get_pi(rdev); > + struct ni_power_info *ni_pi = ni_get_pi(rdev); > PPSMC_Result smc_result; > int ret = 0; > > @@ -2625,7 +2623,7 @@ static int ni_convert_power_state_to_smc(struct radeon_device *rdev, > struct radeon_ps *radeon_state, > NISLANDS_SMC_SWSTATE *smc_state) > { > - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > struct ni_power_info *ni_pi = ni_get_pi(rdev); > struct ni_ps *state = ni_get_ps(radeon_state); > int i, ret; > @@ -2770,46 +2768,46 @@ static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) > bool result = true; > > switch (in_reg) { > - case MC_SEQ_RAS_TIMING >> 2: > + case MC_SEQ_RAS_TIMING >> 2: > *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; > break; > - case MC_SEQ_CAS_TIMING >> 2: > + case MC_SEQ_CAS_TIMING >> 2: > *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; > break; > - case MC_SEQ_MISC_TIMING >> 2: > + case MC_SEQ_MISC_TIMING >> 2: > *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; > break; > - case MC_SEQ_MISC_TIMING2 >> 2: > + case MC_SEQ_MISC_TIMING2 >> 2: > *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; > break; > - case MC_SEQ_RD_CTL_D0 >> 2: > + case MC_SEQ_RD_CTL_D0 >> 2: > *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; > break; > - case MC_SEQ_RD_CTL_D1 >> 2: > + case MC_SEQ_RD_CTL_D1 >> 2: > *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; > break; > - case MC_SEQ_WR_CTL_D0 >> 2: > + case MC_SEQ_WR_CTL_D0 >> 2: > *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; > break; > - case MC_SEQ_WR_CTL_D1 >> 2: > + case MC_SEQ_WR_CTL_D1 >> 2: > *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; > break; > - case MC_PMG_CMD_EMRS >> 2: > + case MC_PMG_CMD_EMRS >> 2: > *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; > break; > - case MC_PMG_CMD_MRS >> 2: > + case MC_PMG_CMD_MRS >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; > break; > - case MC_PMG_CMD_MRS1 >> 2: > + case MC_PMG_CMD_MRS1 >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; > break; > - case MC_SEQ_PMG_TIMING >> 2: > + case MC_SEQ_PMG_TIMING >> 2: > *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; > break; > - case MC_PMG_CMD_MRS2 >> 2: > + case MC_PMG_CMD_MRS2 >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; > break; > - default: > + default: > result = false; > break; > } > @@ -2876,9 +2874,9 @@ static int ni_initialize_mc_reg_table(struct radeon_device *rdev) > struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table; > u8 module_index = rv770_get_memory_module_index(rdev); > > - table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); > - if (!table) > - return -ENOMEM; > + table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); > + if (!table) > + return -ENOMEM; > > WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); > WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); > @@ -2896,25 +2894,25 @@ static int ni_initialize_mc_reg_table(struct radeon_device *rdev) > > ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); > > - if (ret) > - goto init_mc_done; > + if (ret) > + goto init_mc_done; > > ret = ni_copy_vbios_mc_reg_table(table, ni_table); > > - if (ret) > - goto init_mc_done; > + if (ret) > + goto init_mc_done; > > ni_set_s0_mc_reg_index(ni_table); > > ret = ni_set_mc_special_registers(rdev, ni_table); > > - if (ret) > - goto init_mc_done; > + if (ret) > + goto init_mc_done; > > ni_set_valid_flag(ni_table); > > init_mc_done: > - kfree(table); > + kfree(table); > > return ret; > } > @@ -2994,7 +2992,7 @@ static int ni_populate_mc_reg_table(struct radeon_device *rdev, > { > struct rv7xx_power_info *pi = rv770_get_pi(rdev); > struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > - struct ni_power_info *ni_pi = ni_get_pi(rdev); > + struct ni_power_info *ni_pi = ni_get_pi(rdev); > struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); > SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; > > @@ -3025,7 +3023,7 @@ static int ni_upload_mc_reg_table(struct radeon_device *rdev, > { > struct rv7xx_power_info *pi = rv770_get_pi(rdev); > struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > - struct ni_power_info *ni_pi = ni_get_pi(rdev); > + struct ni_power_info *ni_pi = ni_get_pi(rdev); > struct ni_ps *ni_new_state = ni_get_ps(radeon_new_state); > SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; > u16 address; > @@ -3142,7 +3140,7 @@ static int ni_initialize_smc_cac_tables(struct radeon_device *rdev) > struct ni_power_info *ni_pi = ni_get_pi(rdev); > PP_NIslands_CACTABLES *cac_tables = NULL; > int i, ret; > - u32 reg; > + u32 reg; > > if (ni_pi->enable_cac == false) > return 0; > @@ -3422,13 +3420,13 @@ static int ni_pcie_performance_request(struct radeon_device *rdev, > struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > > if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) || > - (perf_req == PCIE_PERF_REQ_PECI_GEN2)) { > + (perf_req == PCIE_PERF_REQ_PECI_GEN2)) { > if (eg_pi->pcie_performance_request_registered == false) > radeon_acpi_pcie_notify_device_ready(rdev); > eg_pi->pcie_performance_request_registered = true; > return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); > } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) && > - eg_pi->pcie_performance_request_registered) { > + eg_pi->pcie_performance_request_registered) { > eg_pi->pcie_performance_request_registered = false; > return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); > } > @@ -3441,12 +3439,12 @@ static int ni_advertise_gen2_capability(struct radeon_device *rdev) > struct rv7xx_power_info *pi = rv770_get_pi(rdev); > u32 tmp; > > - tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); > + tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); > > - if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && > - (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) > - pi->pcie_gen2 = true; > - else > + if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && > + (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) > + pi->pcie_gen2 = true; > + else > pi->pcie_gen2 = false; > > if (!pi->pcie_gen2) > @@ -3458,8 +3456,8 @@ static int ni_advertise_gen2_capability(struct radeon_device *rdev) > static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, > bool enable) > { > - struct rv7xx_power_info *pi = rv770_get_pi(rdev); > - u32 tmp, bif; > + struct rv7xx_power_info *pi = rv770_get_pi(rdev); > + u32 tmp, bif; > > tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); > > @@ -3502,7 +3500,7 @@ static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev, > if (enable) > WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); > else > - WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); > + WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); > } > > void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, > @@ -3563,7 +3561,7 @@ void ni_update_current_ps(struct radeon_device *rdev, > { > struct ni_ps *new_ps = ni_get_ps(rps); > struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > - struct ni_power_info *ni_pi = ni_get_pi(rdev); > + struct ni_power_info *ni_pi = ni_get_pi(rdev); > > eg_pi->current_rps = *rps; > ni_pi->current_ps = *new_ps; > @@ -3575,7 +3573,7 @@ void ni_update_requested_ps(struct radeon_device *rdev, > { > struct ni_ps *new_ps = ni_get_ps(rps); > struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); > - struct ni_power_info *ni_pi = ni_get_pi(rdev); > + struct ni_power_info *ni_pi = ni_get_pi(rdev); > > eg_pi->requested_rps = *rps; > ni_pi->requested_ps = *new_ps; > @@ -3591,8 +3589,8 @@ int ni_dpm_enable(struct radeon_device *rdev) > > if (pi->gfx_clock_gating) > ni_cg_clockgating_default(rdev); > - if (btc_dpm_enabled(rdev)) > - return -EINVAL; > + if (btc_dpm_enabled(rdev)) > + return -EINVAL; > if (pi->mg_clock_gating) > ni_mg_clockgating_default(rdev); > if (eg_pi->ls_clock_gating) > @@ -3991,7 +3989,7 @@ static int ni_parse_power_table(struct radeon_device *rdev) > union pplib_clock_info *clock_info; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > struct ni_ps *ps; > > diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c > index ed12104..f86ab69 100644 > --- a/drivers/gpu/drm/radeon/r600.c > +++ b/drivers/gpu/drm/radeon/r600.c > @@ -235,8 +235,8 @@ int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) > fb_div |= 1; > > r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); > - if (r) > - return r; > + if (r) > + return r; > > /* assert PLL_RESET */ > WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); > @@ -1490,7 +1490,7 @@ static int r600_mc_init(struct radeon_device *rdev) > rdev->fastfb_working = true; > } > } > - } > + } > } > > radeon_update_bandwidth_info(rdev); > @@ -4574,7 +4574,7 @@ uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) > mutex_lock(&rdev->gpu_clock_mutex); > WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); > clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | > - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); > + ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); > mutex_unlock(&rdev->gpu_clock_mutex); > return clock; > } > diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c > index 2f36fa15..b69c8de 100644 > --- a/drivers/gpu/drm/radeon/r600_cs.c > +++ b/drivers/gpu/drm/radeon/r600_cs.c > @@ -1671,8 +1671,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - (idx_value & 0xfffffff0) + > - ((u64)(tmp & 0xff) << 32); > + (idx_value & 0xfffffff0) + > + ((u64)(tmp & 0xff) << 32); > > ib[idx + 0] = offset; > ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); > @@ -1712,8 +1712,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - idx_value + > - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); > + idx_value + > + ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); > > ib[idx+0] = offset; > ib[idx+1] = upper_32_bits(offset) & 0xff; > @@ -1764,8 +1764,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); > ib[idx+2] = upper_32_bits(offset) & 0xff; > @@ -1876,8 +1876,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, > return -EINVAL; > } > offset = reloc->gpu_offset + > - (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = offset & 0xfffffff8; > ib[idx+2] = upper_32_bits(offset) & 0xff; > @@ -1898,8 +1898,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, > } > > offset = reloc->gpu_offset + > - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + > + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); > > ib[idx+1] = offset & 0xfffffffc; > ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); > diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c > index fa21544..6a4b020 100644 > --- a/drivers/gpu/drm/radeon/r600_dpm.c > +++ b/drivers/gpu/drm/radeon/r600_dpm.c > @@ -844,7 +844,7 @@ int r600_get_platform_caps(struct radeon_device *rdev) > struct radeon_mode_info *mode_info = &rdev->mode_info; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > > if (!atom_parse_data_header(mode_info->atom_context, index, NULL, > @@ -874,7 +874,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) > union fan_info *fan_info; > ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > int ret, i; > > @@ -1070,7 +1070,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) > ext_hdr->usVCETableOffset) { > VCEClockInfoArray *array = (VCEClockInfoArray *) > (mode_info->atom_context->bios + data_offset + > - le16_to_cpu(ext_hdr->usVCETableOffset) + 1); > + le16_to_cpu(ext_hdr->usVCETableOffset) + 1); > ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits = > (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *) > (mode_info->atom_context->bios + data_offset + > diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c > index e85894a..e82a99c 100644 > --- a/drivers/gpu/drm/radeon/r600_hdmi.c > +++ b/drivers/gpu/drm/radeon/r600_hdmi.c > @@ -215,7 +215,7 @@ void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, > * build a HDMI Video Info Frame > */ > void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, > - unsigned char *buffer, size_t size) > + unsigned char *buffer, size_t size) > { > uint8_t *frame = buffer + 3; > > @@ -312,7 +312,7 @@ void r600_hdmi_audio_workaround(struct drm_encoder *encoder) > } > > void r600_hdmi_audio_set_dto(struct radeon_device *rdev, > - struct radeon_crtc *crtc, unsigned int clock) > + struct radeon_crtc *crtc, unsigned int clock) > { > struct radeon_encoder *radeon_encoder; > struct radeon_encoder_atom_dig *dig; > diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c > index de9a2ff..f8097a0 100644 > --- a/drivers/gpu/drm/radeon/radeon_atombios.c > +++ b/drivers/gpu/drm/radeon/radeon_atombios.c > @@ -2095,7 +2095,7 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) > struct radeon_i2c_bus_rec i2c_bus; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > > if (!atom_parse_data_header(mode_info->atom_context, index, NULL, > @@ -2575,7 +2575,7 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) > bool valid; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > > if (!atom_parse_data_header(mode_info->atom_context, index, NULL, > @@ -2666,7 +2666,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) > bool valid; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > u8 *power_state_offset; > > diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c > index 4de23ae..ec8de1a 100644 > --- a/drivers/gpu/drm/radeon/radeon_device.c > +++ b/drivers/gpu/drm/radeon/radeon_device.c > @@ -1161,9 +1161,9 @@ static void radeon_check_arguments(struct radeon_device *rdev) > radeon_vm_size = 4; > } > > - /* > - * Max GPUVM size for Cayman, SI and CI are 40 bits. > - */ > + /* > + * Max GPUVM size for Cayman, SI and CI are 40 bits. > + */ > if (radeon_vm_size > 1024) { > dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", > radeon_vm_size); > @@ -1902,7 +1902,7 @@ int radeon_debugfs_add_files(struct radeon_device *rdev, > if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { > DRM_ERROR("Reached maximum number of debugfs components.\n"); > DRM_ERROR("Report so we increase " > - "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); > + "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); > return -EINVAL; > } > rdev->debugfs[rdev->debugfs_count].files = files; > diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c > index a4674bf..150b220 100644 > --- a/drivers/gpu/drm/radeon/radeon_display.c > +++ b/drivers/gpu/drm/radeon/radeon_display.c > @@ -406,7 +406,7 @@ static void radeon_flip_work_func(struct work_struct *__work) > int vpos, hpos, stat, min_udelay; > struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; > > - down_read(&rdev->exclusive_lock); > + down_read(&rdev->exclusive_lock); > if (work->fence) { > struct radeon_fence *fence; > > @@ -906,7 +906,7 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den, > *den /= tmp; > > /* make sure nominator is large enough */ > - if (*nom < nom_min) { > + if (*nom < nom_min) { > tmp = DIV_ROUND_UP(nom_min, *nom); > *nom *= tmp; > *den *= tmp; > @@ -946,7 +946,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, > *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); > > /* limit fb divider to its maximum */ > - if (*fb_div > fb_div_max) { > + if (*fb_div > fb_div_max) { > *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); > *fb_div = fb_div_max; > } > diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c > index d2e628e..4b2c72d 100644 > --- a/drivers/gpu/drm/radeon/radeon_fb.c > +++ b/drivers/gpu/drm/radeon/radeon_fb.c > @@ -38,9 +38,9 @@ > #include <linux/vga_switcheroo.h> > > /* object hierarchy - > - this contains a helper + a radeon fb > - the helper contains a pointer to radeon framebuffer baseclass. > -*/ > + * this contains a helper + a radeon fb > + * the helper contains a pointer to radeon framebuffer baseclass. > + */ > struct radeon_fbdev { > struct drm_fb_helper helper; > struct radeon_framebuffer rfb; > diff --git a/drivers/gpu/drm/radeon/radeon_ib.c b/drivers/gpu/drm/radeon/radeon_ib.c > index c39ce1f..92ce0e5 100644 > --- a/drivers/gpu/drm/radeon/radeon_ib.c > +++ b/drivers/gpu/drm/radeon/radeon_ib.c > @@ -274,7 +274,7 @@ int radeon_ib_ring_tests(struct radeon_device *rdev) > if (i == RADEON_RING_TYPE_GFX_INDEX) { > /* oh, oh, that's really bad */ > DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); > - rdev->accel_working = false; > + rdev->accel_working = false; > return r; > > } else { > @@ -304,7 +304,7 @@ static int radeon_debugfs_sa_info(struct seq_file *m, void *data) > } > > static struct drm_info_list radeon_debugfs_sa_list[] = { > - {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, > + {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, > }; > > #endif > diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c > index 88dc973..868c3ba 100644 > --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c > +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c > @@ -818,52 +818,52 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, > tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & > ~(RADEON_TMDS_TRANSMITTER_PLLRST); > > - if (rdev->family == CHIP_R200 || > - rdev->family == CHIP_R100 || > - ASIC_IS_R300(rdev)) > - tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); > - else /* RV chips got this bit reversed */ > - tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; > - > - fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | > - (RADEON_FP_CRTC_DONT_SHADOW_VPAR | > - RADEON_FP_CRTC_DONT_SHADOW_HEND)); > - > - fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); > - > - fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | > - RADEON_FP_DFP_SYNC_SEL | > - RADEON_FP_CRT_SYNC_SEL | > - RADEON_FP_CRTC_LOCK_8DOT | > - RADEON_FP_USE_SHADOW_EN | > - RADEON_FP_CRTC_USE_SHADOW_VEND | > - RADEON_FP_CRT_SYNC_ALT); > - > - if (1) /* FIXME rgbBits == 8 */ > - fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ > - else > - fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ > - > - if (radeon_crtc->crtc_id == 0) { > - if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { > - fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; > - if (radeon_encoder->rmx_type != RMX_OFF) > - fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; > - else > - fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; > - } else > - fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; > - } else { > - if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { > - fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; > - fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; > - } else > - fp_gen_cntl |= RADEON_FP_SEL_CRTC2; > - } > - > - WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); > - WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); > - WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); > + if (rdev->family == CHIP_R200 || > + rdev->family == CHIP_R100 || > + ASIC_IS_R300(rdev)) > + tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); > + else /* RV chips got this bit reversed */ > + tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; > + > + fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | > + (RADEON_FP_CRTC_DONT_SHADOW_VPAR | > + RADEON_FP_CRTC_DONT_SHADOW_HEND)); > + > + fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); > + > + fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | > + RADEON_FP_DFP_SYNC_SEL | > + RADEON_FP_CRT_SYNC_SEL | > + RADEON_FP_CRTC_LOCK_8DOT | > + RADEON_FP_USE_SHADOW_EN | > + RADEON_FP_CRTC_USE_SHADOW_VEND | > + RADEON_FP_CRT_SYNC_ALT); > + > + if (1) /* FIXME rgbBits == 8 */ > + fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ > + else > + fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ > + > + if (radeon_crtc->crtc_id == 0) { > + if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { > + fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; > + if (radeon_encoder->rmx_type != RMX_OFF) > + fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; > + else > + fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; > + } else > + fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; > + } else { > + if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { > + fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; > + fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; > + } else > + fp_gen_cntl |= RADEON_FP_SEL_CRTC2; > + } > + > + WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); > + WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); > + WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); > > if (rdev->is_atom_bios) > radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); > diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c > index fb6ad14..dd46c38 100644 > --- a/drivers/gpu/drm/radeon/radeon_object.c > +++ b/drivers/gpu/drm/radeon/radeon_object.c > @@ -214,8 +214,8 @@ int radeon_bo_create(struct radeon_device *rdev, > INIT_LIST_HEAD(&bo->list); > INIT_LIST_HEAD(&bo->va); > bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | > - RADEON_GEM_DOMAIN_GTT | > - RADEON_GEM_DOMAIN_CPU); > + RADEON_GEM_DOMAIN_GTT | > + RADEON_GEM_DOMAIN_CPU); > > bo->flags = flags; > /* PCI GART is always snooped */ > @@ -848,7 +848,7 @@ int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) > * > */ > void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, > - bool shared) > + bool shared) > { > struct reservation_object *resv = bo->tbo.resv; > > diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c > index 460c8f2..3748a62 100644 > --- a/drivers/gpu/drm/radeon/radeon_pm.c > +++ b/drivers/gpu/drm/radeon/radeon_pm.c > @@ -79,7 +79,7 @@ void radeon_pm_acpi_event_handler(struct radeon_device *rdev) > radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); > } > mutex_unlock(&rdev->pm.mutex); > - } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { > + } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { > if (rdev->pm.profile == PM_PROFILE_AUTO) { > mutex_lock(&rdev->pm.mutex); > radeon_pm_update_profile(rdev); > diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c > index e6ad54c..b0eb28e 100644 > --- a/drivers/gpu/drm/radeon/radeon_semaphore.c > +++ b/drivers/gpu/drm/radeon/radeon_semaphore.c > @@ -56,7 +56,7 @@ int radeon_semaphore_create(struct radeon_device *rdev, > } > > bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ridx, > - struct radeon_semaphore *semaphore) > + struct radeon_semaphore *semaphore) > { > struct radeon_ring *ring = &rdev->ring[ridx]; > > @@ -73,7 +73,7 @@ bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ridx, > } > > bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ridx, > - struct radeon_semaphore *semaphore) > + struct radeon_semaphore *semaphore) > { > struct radeon_ring *ring = &rdev->ring[ridx]; > > diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c > index 6edcb54..6fe9e4e 100644 > --- a/drivers/gpu/drm/radeon/radeon_uvd.c > +++ b/drivers/gpu/drm/radeon/radeon_uvd.c > @@ -722,9 +722,11 @@ static int radeon_uvd_send_msg(struct radeon_device *rdev, > return r; > } > > -/* multiple fence commands without any stream commands in between can > - crash the vcpu so just try to emmit a dummy create/destroy msg to > - avoid this */ > +/* > + * multiple fence commands without any stream commands in between can > + * crash the vcpu so just try to emmit a dummy create/destroy msg to > + * avoid this > + */ > int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, > uint32_t handle, struct radeon_fence **fence) > { > diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c > index 566a1a0..c1c619f 100644 > --- a/drivers/gpu/drm/radeon/radeon_vce.c > +++ b/drivers/gpu/drm/radeon/radeon_vce.c > @@ -166,7 +166,7 @@ int radeon_vce_init(struct radeon_device *rdev) > for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { > atomic_set(&rdev->vce.handles[i], 0); > rdev->vce.filp[i] = NULL; > - } > + } > > return 0; > } > @@ -389,7 +389,7 @@ int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, > > r = radeon_ib_schedule(rdev, &ib, NULL, false); > if (r) { > - DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); > + DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); > } > > if (fence) > @@ -446,7 +446,7 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, > > r = radeon_ib_schedule(rdev, &ib, NULL, false); > if (r) { > - DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); > + DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); > } > > if (fence) > @@ -769,18 +769,18 @@ int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) > radeon_ring_unlock_commit(rdev, ring, false); > > for (i = 0; i < rdev->usec_timeout; i++) { > - if (vce_v1_0_get_rptr(rdev, ring) != rptr) > - break; > - DRM_UDELAY(1); > + if (vce_v1_0_get_rptr(rdev, ring) != rptr) > + break; > + DRM_UDELAY(1); > } > > if (i < rdev->usec_timeout) { > - DRM_INFO("ring test on %d succeeded in %d usecs\n", > - ring->idx, i); > + DRM_INFO("ring test on %d succeeded in %d usecs\n", > + ring->idx, i); > } else { > - DRM_ERROR("radeon: ring %d test failed\n", > - ring->idx); > - r = -ETIMEDOUT; > + DRM_ERROR("radeon: ring %d test failed\n", > + ring->idx); > + r = -ETIMEDOUT; > } > > return r; > diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c > index 3979632..a135874 100644 > --- a/drivers/gpu/drm/radeon/radeon_vm.c > +++ b/drivers/gpu/drm/radeon/radeon_vm.c > @@ -611,15 +611,16 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr) > */ > static uint32_t radeon_vm_page_flags(uint32_t flags) > { > - uint32_t hw_flags = 0; > - hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0; > - hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; > - hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; > - if (flags & RADEON_VM_PAGE_SYSTEM) { > - hw_flags |= R600_PTE_SYSTEM; > - hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; > - } > - return hw_flags; > + uint32_t hw_flags = 0; > + > + hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0; > + hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; > + hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; > + if (flags & RADEON_VM_PAGE_SYSTEM) { > + hw_flags |= R600_PTE_SYSTEM; > + hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; > + } > + return hw_flags; > } > > /** > diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c > index cb0afe7..94b48fc 100644 > --- a/drivers/gpu/drm/radeon/rs780_dpm.c > +++ b/drivers/gpu/drm/radeon/rs780_dpm.c > @@ -795,7 +795,7 @@ static int rs780_parse_power_table(struct radeon_device *rdev) > union pplib_clock_info *clock_info; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > struct igp_ps *ps; > > diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c > index 97e5a6f..25e2930 100644 > --- a/drivers/gpu/drm/radeon/rv6xx_dpm.c > +++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c > @@ -209,7 +209,7 @@ static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev > > static bool rv6xx_can_step_post_div(struct radeon_device *rdev, > struct rv6xx_sclk_stepping *cur, > - struct rv6xx_sclk_stepping *target) > + struct rv6xx_sclk_stepping *target) > { > return (cur->post_divider > target->post_divider) && > ((cur->vco_frequency * target->post_divider) <= > @@ -239,7 +239,7 @@ static bool rv6xx_reached_stepping_target(struct radeon_device *rdev, > > static void rv6xx_generate_steps(struct radeon_device *rdev, > u32 low, u32 high, > - u32 start_index, u8 *end_index) > + u32 start_index, u8 *end_index) > { > struct rv6xx_sclk_stepping cur; > struct rv6xx_sclk_stepping target; > @@ -1356,23 +1356,23 @@ static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) > enum radeon_dpm_event_src dpm_event_src; > > switch (sources) { > - case 0: > - default: > + case 0: > + default: > want_thermal_protection = false; > break; > - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): > + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): > want_thermal_protection = true; > dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; > break; > > - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): > + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): > want_thermal_protection = true; > dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; > break; > > - case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | > + case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | > (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): > - want_thermal_protection = true; > + want_thermal_protection = true; > dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; > break; > } > @@ -1879,7 +1879,7 @@ static int rv6xx_parse_power_table(struct radeon_device *rdev) > union pplib_clock_info *clock_info; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > struct rv6xx_ps *ps; > > diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c b/drivers/gpu/drm/radeon/rv740_dpm.c > index c4c8da5..4b85082 100644 > --- a/drivers/gpu/drm/radeon/rv740_dpm.c > +++ b/drivers/gpu/drm/radeon/rv740_dpm.c > @@ -36,28 +36,28 @@ u32 rv740_get_decoded_reference_divider(u32 encoded_ref) > u32 ref = 0; > > switch (encoded_ref) { > - case 0: > + case 0: > ref = 1; > break; > - case 16: > + case 16: > ref = 2; > break; > - case 17: > + case 17: > ref = 3; > break; > - case 18: > + case 18: > ref = 2; > break; > - case 19: > + case 19: > ref = 3; > break; > - case 20: > + case 20: > ref = 4; > break; > - case 21: > + case 21: > ref = 5; > break; > - default: > + default: > DRM_ERROR("Invalid encoded Reference Divider\n"); > ref = 0; > break; > diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c > index e830c89..a010dec 100644 > --- a/drivers/gpu/drm/radeon/rv770_dpm.c > +++ b/drivers/gpu/drm/radeon/rv770_dpm.c > @@ -345,27 +345,27 @@ static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) > int ret = 0; > > switch (postdiv) { > - case 1: > + case 1: > *encoded_postdiv = 0; > break; > - case 2: > + case 2: > *encoded_postdiv = 1; > break; > - case 4: > + case 4: > *encoded_postdiv = 2; > break; > - case 8: > + case 8: > *encoded_postdiv = 3; > break; > - case 16: > + case 16: > *encoded_postdiv = 4; > break; > - default: > + default: > ret = -EINVAL; > break; > } > > - return ret; > + return ret; > } > > u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf) > @@ -1175,15 +1175,15 @@ static int rv770_init_smc_table(struct radeon_device *rdev, > rv770_populate_smc_mvdd_table(rdev, table); > > switch (rdev->pm.int_thermal_type) { > - case THERMAL_TYPE_RV770: > - case THERMAL_TYPE_ADT7473_WITH_INTERNAL: > + case THERMAL_TYPE_RV770: > + case THERMAL_TYPE_ADT7473_WITH_INTERNAL: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; > break; > - case THERMAL_TYPE_NONE: > + case THERMAL_TYPE_NONE: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; > break; > - case THERMAL_TYPE_EXTERNAL_GPIO: > - default: > + case THERMAL_TYPE_EXTERNAL_GPIO: > + default: > table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; > break; > } > @@ -1567,18 +1567,18 @@ void rv770_reset_smio_status(struct radeon_device *rdev) > sw_smio_index = > (RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT; > switch (sw_smio_index) { > - case 3: > + case 3: > vid_smio_cntl = RREG32(S3_VID_LOWER_SMIO_CNTL); > break; > - case 2: > + case 2: > vid_smio_cntl = RREG32(S2_VID_LOWER_SMIO_CNTL); > break; > - case 1: > + case 1: > vid_smio_cntl = RREG32(S1_VID_LOWER_SMIO_CNTL); > break; > - case 0: > + case 0: > return; > - default: > + default: > vid_smio_cntl = pi->s0_vid_lower_smio_cntl; > break; > } > @@ -1817,21 +1817,21 @@ static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) > enum radeon_dpm_event_src dpm_event_src; > > switch (sources) { > - case 0: > - default: > + case 0: > + default: > want_thermal_protection = false; > break; > - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): > + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): > want_thermal_protection = true; > dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; > break; > > - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): > + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): > want_thermal_protection = true; > dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; > break; > > - case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | > + case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | > (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): > want_thermal_protection = true; > dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; > @@ -2273,7 +2273,7 @@ int rv7xx_parse_power_table(struct radeon_device *rdev) > union pplib_clock_info *clock_info; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > struct rv7xx_ps *ps; > > diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c > index f878d69..e894be2 100644 > --- a/drivers/gpu/drm/radeon/si.c > +++ b/drivers/gpu/drm/radeon/si.c > @@ -1307,7 +1307,7 @@ int si_get_allowed_info_register(struct radeon_device *rdev, > */ > u32 si_get_xclk(struct radeon_device *rdev) > { > - u32 reference_clock = rdev->clock.spll.reference_freq; > + u32 reference_clock = rdev->clock.spll.reference_freq; > u32 tmp; > > tmp = RREG32(CG_CLKPIN_CNTL_2); > @@ -7314,7 +7314,7 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev) > mutex_lock(&rdev->gpu_clock_mutex); > WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); > clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | > - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); > + ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); > mutex_unlock(&rdev->gpu_clock_mutex); > return clock; > } > @@ -7775,33 +7775,33 @@ static void si_program_aspm(struct radeon_device *rdev) > > int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev) > { > - unsigned i; > + unsigned i; > > - /* make sure VCEPLL_CTLREQ is deasserted */ > - WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); > + /* make sure VCEPLL_CTLREQ is deasserted */ > + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); > > - mdelay(10); > + mdelay(10); > > - /* assert UPLL_CTLREQ */ > - WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); > + /* assert UPLL_CTLREQ */ > + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); > > - /* wait for CTLACK and CTLACK2 to get asserted */ > - for (i = 0; i < 100; ++i) { > - uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; > - if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) > - break; > - mdelay(10); > - } > + /* wait for CTLACK and CTLACK2 to get asserted */ > + for (i = 0; i < 100; ++i) { > + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; > + if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) > + break; > + mdelay(10); > + } > > - /* deassert UPLL_CTLREQ */ > - WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); > + /* deassert UPLL_CTLREQ */ > + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); > > - if (i == 100) { > - DRM_ERROR("Timeout setting UVD clocks!\n"); > - return -ETIMEDOUT; > - } > + if (i == 100) { > + DRM_ERROR("Timeout setting UVD clocks!\n"); > + return -ETIMEDOUT; > + } > > - return 0; > + return 0; > } > > int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) > diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c > index a82b891..cb75ab7 100644 > --- a/drivers/gpu/drm/radeon/si_dpm.c > +++ b/drivers/gpu/drm/radeon/si_dpm.c > @@ -499,7 +499,7 @@ static const struct si_cac_config_reg lcac_pitcairn[] = > > static const struct si_cac_config_reg cac_override_pitcairn[] = > { > - { 0xFFFFFFFF } > + { 0xFFFFFFFF } > }; > > static const struct si_powertune_data powertune_data_pitcairn = > @@ -991,7 +991,7 @@ static const struct si_cac_config_reg lcac_cape_verde[] = > > static const struct si_cac_config_reg cac_override_cape_verde[] = > { > - { 0xFFFFFFFF } > + { 0xFFFFFFFF } > }; > > static const struct si_powertune_data powertune_data_cape_verde = > @@ -1762,9 +1762,9 @@ static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); > > static struct si_power_info *si_get_pi(struct radeon_device *rdev) > { > - struct si_power_info *pi = rdev->pm.dpm.priv; > + struct si_power_info *pi = rdev->pm.dpm.priv; > > - return pi; > + return pi; > } > > static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, > @@ -3150,9 +3150,9 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, > } > } > > - for (i = 0; i < ps->performance_level_count; i++) > - btc_adjust_clock_combinations(rdev, max_limits, > - &ps->performance_levels[i]); > + for (i = 0; i < ps->performance_level_count; i++) > + btc_adjust_clock_combinations(rdev, max_limits, > + &ps->performance_levels[i]); > > for (i = 0; i < ps->performance_level_count; i++) { > if (ps->performance_levels[i].vddc < min_vce_voltage) > @@ -3291,7 +3291,7 @@ static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) > case 0: > default: > want_thermal_protection = false; > - break; > + break; > case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): > want_thermal_protection = true; > dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; > @@ -3493,7 +3493,7 @@ static int si_process_firmware_header(struct radeon_device *rdev) > if (ret) > return ret; > > - si_pi->state_table_start = tmp; > + si_pi->state_table_start = tmp; > > ret = si_read_smc_sram_dword(rdev, > SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + > @@ -3652,7 +3652,7 @@ static void si_program_response_times(struct radeon_device *rdev) > si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); > > voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; > - backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; > + backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; > > if (voltage_response_time == 0) > voltage_response_time = 1000; > @@ -3760,7 +3760,7 @@ static void si_setup_bsp(struct radeon_device *rdev) > &pi->pbsu); > > > - pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); > + pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); > pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); > > WREG32(CG_BSP, pi->dsp); > @@ -4308,7 +4308,7 @@ static int si_populate_memory_timing_parameters(struct radeon_device *rdev, > > radeon_atom_set_engine_dram_timings(rdev, > pl->sclk, > - pl->mclk); > + pl->mclk); > > dram_timing = RREG32(MC_ARB_DRAM_TIMING); > dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); > @@ -4343,7 +4343,7 @@ static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, > si_pi->sram_end); > if (ret) > break; > - } > + } > > return ret; > } > @@ -4821,9 +4821,9 @@ static int si_calculate_sclk_params(struct radeon_device *rdev, > spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; > spll_func_cntl_2 |= SCLK_MUX_SEL(2); > > - spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; > - spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); > - spll_func_cntl_3 |= SPLL_DITHEN; > + spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; > + spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); > + spll_func_cntl_3 |= SPLL_DITHEN; > > if (pi->sclk_ss) { > struct radeon_atom_ss ss; > @@ -4930,15 +4930,15 @@ static int si_populate_mclk_value(struct radeon_device *rdev, > tmp = freq_nom / reference_clock; > tmp = tmp * tmp; > if (radeon_atombios_get_asic_ss_info(rdev, &ss, > - ASIC_INTERNAL_MEMORY_SS, freq_nom)) { > + ASIC_INTERNAL_MEMORY_SS, freq_nom)) { > u32 clks = reference_clock * 5 / ss.rate; > u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); > > - mpll_ss1 &= ~CLKV_MASK; > - mpll_ss1 |= CLKV(clkv); > + mpll_ss1 &= ~CLKV_MASK; > + mpll_ss1 |= CLKV(clkv); > > - mpll_ss2 &= ~CLKS_MASK; > - mpll_ss2 |= CLKS(clks); > + mpll_ss2 &= ~CLKS_MASK; > + mpll_ss2 |= CLKS(clks); > } > } > > @@ -5265,7 +5265,7 @@ static int si_convert_power_state_to_smc(struct radeon_device *rdev, > ni_pi->enable_power_containment = false; > > ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); > - if (ret) > + if (ret) > ni_pi->enable_sq_ramping = false; > > return si_populate_smc_t(rdev, radeon_state, smc_state); > @@ -5436,46 +5436,46 @@ static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) > case MC_SEQ_RAS_TIMING >> 2: > *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; > break; > - case MC_SEQ_CAS_TIMING >> 2: > + case MC_SEQ_CAS_TIMING >> 2: > *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; > break; > - case MC_SEQ_MISC_TIMING >> 2: > + case MC_SEQ_MISC_TIMING >> 2: > *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; > break; > - case MC_SEQ_MISC_TIMING2 >> 2: > + case MC_SEQ_MISC_TIMING2 >> 2: > *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; > break; > - case MC_SEQ_RD_CTL_D0 >> 2: > + case MC_SEQ_RD_CTL_D0 >> 2: > *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; > break; > - case MC_SEQ_RD_CTL_D1 >> 2: > + case MC_SEQ_RD_CTL_D1 >> 2: > *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; > break; > - case MC_SEQ_WR_CTL_D0 >> 2: > + case MC_SEQ_WR_CTL_D0 >> 2: > *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; > break; > - case MC_SEQ_WR_CTL_D1 >> 2: > + case MC_SEQ_WR_CTL_D1 >> 2: > *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; > break; > - case MC_PMG_CMD_EMRS >> 2: > + case MC_PMG_CMD_EMRS >> 2: > *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; > break; > - case MC_PMG_CMD_MRS >> 2: > + case MC_PMG_CMD_MRS >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; > break; > - case MC_PMG_CMD_MRS1 >> 2: > + case MC_PMG_CMD_MRS1 >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; > break; > - case MC_SEQ_PMG_TIMING >> 2: > + case MC_SEQ_PMG_TIMING >> 2: > *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; > break; > - case MC_PMG_CMD_MRS2 >> 2: > + case MC_PMG_CMD_MRS2 >> 2: > *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; > break; > - case MC_SEQ_WR_CTL_2 >> 2: > + case MC_SEQ_WR_CTL_2 >> 2: > *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; > break; > - default: > + default: > result = false; > break; > } > @@ -5562,19 +5562,19 @@ static int si_initialize_mc_reg_table(struct radeon_device *rdev) > WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); > WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); > > - ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); > - if (ret) > - goto init_mc_done; > + ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); > + if (ret) > + goto init_mc_done; > > - ret = si_copy_vbios_mc_reg_table(table, si_table); > - if (ret) > - goto init_mc_done; > + ret = si_copy_vbios_mc_reg_table(table, si_table); > + if (ret) > + goto init_mc_done; > > si_set_s0_mc_reg_index(si_table); > > ret = si_set_mc_special_registers(rdev, si_table); > - if (ret) > - goto init_mc_done; > + if (ret) > + goto init_mc_done; > > si_set_valid_flag(si_table); > > @@ -5715,10 +5715,10 @@ static int si_upload_mc_reg_table(struct radeon_device *rdev, > > static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) > { > - if (enable) > - WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); > - else > - WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); > + if (enable) > + WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); > + else > + WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); > } > > static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, > @@ -6820,7 +6820,7 @@ static int si_parse_power_table(struct radeon_device *rdev) > struct _NonClockInfoArray *non_clock_info_array; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > u8 *power_state_offset; > struct ni_ps *ps; > diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c > index cd08628..f0d5c17 100644 > --- a/drivers/gpu/drm/radeon/sumo_dpm.c > +++ b/drivers/gpu/drm/radeon/sumo_dpm.c > @@ -787,8 +787,8 @@ static void sumo_program_acpi_power_level(struct radeon_device *rdev) > struct atom_clock_dividers dividers; > int ret; > > - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > - pi->acpi_pl.sclk, > + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > + pi->acpi_pl.sclk, > false, &dividers); > if (ret) > return; > @@ -1462,7 +1462,7 @@ static int sumo_parse_power_table(struct radeon_device *rdev) > struct _NonClockInfoArray *non_clock_info_array; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > u8 *power_state_offset; > struct sumo_ps *ps; > diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c > index d34bfcda..6730367 100644 > --- a/drivers/gpu/drm/radeon/trinity_dpm.c > +++ b/drivers/gpu/drm/radeon/trinity_dpm.c > @@ -369,8 +369,8 @@ static void trinity_gfx_powergating_initialize(struct radeon_device *rdev) > int ret; > u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; > > - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > - 25000, false, &dividers); > + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > + 25000, false, &dividers); > if (ret) > return; > > @@ -587,8 +587,8 @@ static void trinity_set_divider_value(struct radeon_device *rdev, > u32 value; > u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; > > - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > - sclk, false, &dividers); > + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > + sclk, false, &dividers); > if (ret) > return; > > @@ -597,8 +597,8 @@ static void trinity_set_divider_value(struct radeon_device *rdev, > value |= CLK_DIVIDER(dividers.post_div); > WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); > > - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > - sclk/2, false, &dividers); > + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, > + sclk/2, false, &dividers); > if (ret) > return; > > @@ -1045,14 +1045,14 @@ static int trinity_set_thermal_temperature_range(struct radeon_device *rdev, > int low_temp = 0 * 1000; > int high_temp = 255 * 1000; > > - if (low_temp < min_temp) > + if (low_temp < min_temp) > low_temp = min_temp; > - if (high_temp > max_temp) > + if (high_temp > max_temp) > high_temp = max_temp; > - if (high_temp < low_temp) { > + if (high_temp < low_temp) { > DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); > - return -EINVAL; > - } > + return -EINVAL; > + } > > WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); > WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); > @@ -1737,7 +1737,7 @@ static int trinity_parse_power_table(struct radeon_device *rdev) > struct _NonClockInfoArray *non_clock_info_array; > union power_info *power_info; > int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); > - u16 data_offset; > + u16 data_offset; > u8 frev, crev; > u8 *power_state_offset; > struct sumo_ps *ps; > diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c > index cdeaab7..fce2144 100644 > --- a/drivers/gpu/drm/radeon/vce_v2_0.c > +++ b/drivers/gpu/drm/radeon/vce_v2_0.c > @@ -53,7 +53,7 @@ static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) > WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); > > WREG32(VCE_CGTT_CLK_OVERRIDE, 0); > - } else { > + } else { > tmp = RREG32(VCE_CLOCK_GATING_B); > tmp |= 0xe7; > tmp &= ~0xe70000;

diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c index ec1593a..f66c33d 100644 --- a/drivers/gpu/drm/radeon/atom.c +++ b/drivers/gpu/drm/radeon/atom.c @@ -66,9 +66,10 @@ int atom_debug = 0; static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); -static uint32_t atom_arg_mask[8] = - { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, -0xFF000000 }; +static uint32_t atom_arg_mask[8] = { + 0xFFFFFFFF, 0x0000FFFF, 0x00FFFF00, 0xFFFF0000, + 0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000 +}; static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; static int atom_dst_to_src[8][4] = { diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index e187bec..cf61e08 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1665,11 +1665,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, } int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, + struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state) { - struct drm_device *dev = crtc->dev; - struct radeon_device *rdev = dev->dev_private; + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; if (ASIC_IS_DCE4(rdev)) return dce4_crtc_do_set_base(crtc, fb, x, y, 1); diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 44ee72e..ae1ab4d 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -37,10 +37,10 @@ #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE static char *voltage_names[] = { - "0.4V", "0.6V", "0.8V", "1.2V" + "0.4V", "0.6V", "0.8V", "1.2V" }; static char *pre_emph_names[] = { - "0dB", "3.5dB", "6dB", "9.5dB" + "0dB", "3.5dB", "6dB", "9.5dB" }; /***** radeon AUX functions *****/ diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c index 69556f5..38e5123 100644 --- a/drivers/gpu/drm/radeon/btc_dpm.c +++ b/drivers/gpu/drm/radeon/btc_dpm.c @@ -1163,12 +1163,11 @@ u32 btc_valid_sclk[40] = 155000, 160000, 165000, 170000, 175000, 180000, 185000, 190000, 195000, 200000 }; -static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = -{ - { 10000, 30000, RADEON_SCLK_UP }, - { 15000, 30000, RADEON_SCLK_UP }, - { 20000, 30000, RADEON_SCLK_UP }, - { 25000, 30000, RADEON_SCLK_UP } +static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = { + { 10000, 30000, RADEON_SCLK_UP }, + { 15000, 30000, RADEON_SCLK_UP }, + { 20000, 30000, RADEON_SCLK_UP }, + { 25000, 30000, RADEON_SCLK_UP } }; void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, @@ -1637,14 +1636,14 @@ static int btc_init_smc_table(struct radeon_device *rdev, cypress_populate_smc_voltage_tables(rdev, table); switch (rdev->pm.int_thermal_type) { - case THERMAL_TYPE_EVERGREEN: - case THERMAL_TYPE_EMC2103_WITH_INTERNAL: + case THERMAL_TYPE_EVERGREEN: + case THERMAL_TYPE_EMC2103_WITH_INTERNAL: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; break; - case THERMAL_TYPE_NONE: + case THERMAL_TYPE_NONE: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; break; - default: + default: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; break; } @@ -1860,37 +1859,37 @@ static bool btc_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) case MC_SEQ_RAS_TIMING >> 2: *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; break; - case MC_SEQ_CAS_TIMING >> 2: + case MC_SEQ_CAS_TIMING >> 2: *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; break; - case MC_SEQ_MISC_TIMING >> 2: + case MC_SEQ_MISC_TIMING >> 2: *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; break; - case MC_SEQ_MISC_TIMING2 >> 2: + case MC_SEQ_MISC_TIMING2 >> 2: *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; break; - case MC_SEQ_RD_CTL_D0 >> 2: + case MC_SEQ_RD_CTL_D0 >> 2: *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; break; - case MC_SEQ_RD_CTL_D1 >> 2: + case MC_SEQ_RD_CTL_D1 >> 2: *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; break; - case MC_SEQ_WR_CTL_D0 >> 2: + case MC_SEQ_WR_CTL_D0 >> 2: *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; break; - case MC_SEQ_WR_CTL_D1 >> 2: + case MC_SEQ_WR_CTL_D1 >> 2: *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; break; - case MC_PMG_CMD_EMRS >> 2: + case MC_PMG_CMD_EMRS >> 2: *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; break; - case MC_PMG_CMD_MRS >> 2: + case MC_PMG_CMD_MRS >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; break; - case MC_PMG_CMD_MRS1 >> 2: + case MC_PMG_CMD_MRS1 >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; break; - default: + default: result = false; break; } diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 4a09947..35e0fc3 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -192,9 +192,9 @@ static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev); static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) { - struct ci_power_info *pi = rdev->pm.dpm.priv; + struct ci_power_info *pi = rdev->pm.dpm.priv; - return pi; + return pi; } static struct ci_ps *ci_get_ps(struct radeon_ps *rps) @@ -1632,7 +1632,7 @@ static int ci_notify_hw_of_power_source(struct radeon_device *rdev, else power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); - ci_set_power_limit(rdev, power_limit); + ci_set_power_limit(rdev, power_limit); if (pi->caps_automatic_dc_transition) { if (ac_power) @@ -2017,9 +2017,9 @@ static void ci_enable_display_gap(struct radeon_device *rdev) { u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL); - tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); - tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | - DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); + tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK); + tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) | + DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK)); WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); } @@ -2938,8 +2938,8 @@ static int ci_populate_single_memory_level(struct radeon_device *rdev, memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); - memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); - memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); + memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); + memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); @@ -3152,7 +3152,7 @@ static int ci_calculate_sclk_params(struct radeon_device *rdev, spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); - spll_func_cntl_3 |= SPLL_DITHEN; + spll_func_cntl_3 |= SPLL_DITHEN; if (pi->caps_sclk_ss_support) { struct radeon_atom_ss ss; @@ -3229,7 +3229,7 @@ static int ci_populate_single_graphic_level(struct radeon_device *rdev, graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; graphic_level->Flags = cpu_to_be32(graphic_level->Flags); - graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); + graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); @@ -4393,7 +4393,7 @@ static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) break; case MC_SEQ_CAS_TIMING >> 2: *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; - break; + break; case MC_SEQ_MISC_TIMING >> 2: *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; break; @@ -4625,7 +4625,7 @@ static int ci_initialize_mc_reg_table(struct radeon_device *rdev) if (ret) goto init_mc_done; - ret = ci_copy_vbios_mc_reg_table(table, ci_table); + ret = ci_copy_vbios_mc_reg_table(table, ci_table); if (ret) goto init_mc_done; @@ -4916,7 +4916,7 @@ static int ci_set_private_data_variables_based_on_pptable(struct radeon_device * allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; - rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = + rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; return 0; @@ -5517,7 +5517,7 @@ static int ci_parse_power_table(struct radeon_device *rdev) struct _NonClockInfoArray *non_clock_info_array; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; u8 *power_state_offset; struct ci_ps *ps; @@ -5693,8 +5693,8 @@ int ci_dpm_init(struct radeon_device *rdev) return ret; } - pi->dll_default_on = false; - pi->sram_end = SMC_RAM_END; + pi->dll_default_on = false; + pi->sram_end = SMC_RAM_END; pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; @@ -5734,9 +5734,9 @@ int ci_dpm_init(struct radeon_device *rdev) pi->caps_uvd_dpm = true; pi->caps_vce_dpm = true; - ci_get_leakage_voltages(rdev); - ci_patch_dependency_tables_with_leakage(rdev); - ci_set_private_data_variables_based_on_pptable(rdev); + ci_get_leakage_voltages(rdev); + ci_patch_dependency_tables_with_leakage(rdev); + ci_set_private_data_variables_based_on_pptable(rdev); rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); @@ -5839,7 +5839,7 @@ int ci_dpm_init(struct radeon_device *rdev) pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; else rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; - } + } if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) @@ -5860,7 +5860,7 @@ int ci_dpm_init(struct radeon_device *rdev) #endif if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, - &frev, &crev, &data_offset)) { + &frev, &crev, &data_offset)) { pi->caps_sclk_ss_support = true; pi->caps_mclk_ss_support = true; pi->dynamic_ss = true; diff --git a/drivers/gpu/drm/radeon/ci_smc.c b/drivers/gpu/drm/radeon/ci_smc.c index 35c6f64..24760ee 100644 --- a/drivers/gpu/drm/radeon/ci_smc.c +++ b/drivers/gpu/drm/radeon/ci_smc.c @@ -194,11 +194,11 @@ PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev) return PPSMC_Result_OK; for (i = 0; i < rdev->usec_timeout; i++) { - tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); - if ((tmp & CKEN) == 0) + tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); + if ((tmp & CKEN) == 0) break; - udelay(1); - } + udelay(1); + } return PPSMC_Result_OK; } diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 0600140..f2a4c0f 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -1712,7 +1712,7 @@ static void cik_init_golden_registers(struct radeon_device *rdev) */ u32 cik_get_xclk(struct radeon_device *rdev) { - u32 reference_clock = rdev->clock.spll.reference_freq; + u32 reference_clock = rdev->clock.spll.reference_freq; if (rdev->flags & RADEON_IS_IGP) { if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) @@ -9709,13 +9709,13 @@ uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev) mutex_lock(&rdev->gpu_clock_mutex); WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); + ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); mutex_unlock(&rdev->gpu_clock_mutex); return clock; } static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock, - u32 cntl_reg, u32 status_reg) + u32 cntl_reg, u32 status_reg) { int r, i; struct atom_clock_dividers dividers; diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c index ca05858..a4edd07 100644 --- a/drivers/gpu/drm/radeon/cypress_dpm.c +++ b/drivers/gpu/drm/radeon/cypress_dpm.c @@ -1620,14 +1620,14 @@ static int cypress_init_smc_table(struct radeon_device *rdev, cypress_populate_smc_voltage_tables(rdev, table); switch (rdev->pm.int_thermal_type) { - case THERMAL_TYPE_EVERGREEN: - case THERMAL_TYPE_EMC2103_WITH_INTERNAL: + case THERMAL_TYPE_EVERGREEN: + case THERMAL_TYPE_EMC2103_WITH_INTERNAL: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; break; - case THERMAL_TYPE_NONE: + case THERMAL_TYPE_NONE: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; break; - default: + default: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; break; } diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 2ad4628..76c4bdf 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1140,7 +1140,7 @@ static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock, int r, i; struct atom_clock_dividers dividers; - r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers); if (r) return r; diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c index 46f87d4..9e93205 100644 --- a/drivers/gpu/drm/radeon/evergreen_cs.c +++ b/drivers/gpu/drm/radeon/evergreen_cs.c @@ -1816,8 +1816,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - (idx_value & 0xfffffff0) + - ((u64)(tmp & 0xff) << 32); + (idx_value & 0xfffffff0) + + ((u64)(tmp & 0xff) << 32); ib[idx + 0] = offset; ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); @@ -1862,8 +1862,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - idx_value + - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); + idx_value + + ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); ib[idx+0] = offset; ib[idx+1] = upper_32_bits(offset) & 0xff; @@ -1897,8 +1897,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - idx_value + - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); + idx_value + + ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); ib[idx+0] = offset; ib[idx+1] = upper_32_bits(offset) & 0xff; @@ -1925,8 +1925,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - radeon_get_ib_value(p, idx+1) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + radeon_get_ib_value(p, idx+1) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = offset; ib[idx+2] = upper_32_bits(offset) & 0xff; @@ -2098,8 +2098,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); ib[idx+2] = upper_32_bits(offset) & 0xff; @@ -2239,8 +2239,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } offset = reloc->gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = offset & 0xfffffff8; ib[idx+2] = upper_32_bits(offset) & 0xff; @@ -2261,8 +2261,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = offset & 0xfffffffc; ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); @@ -2283,8 +2283,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = offset & 0xfffffffc; ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index 3cf04a2..f766c96 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c @@ -206,7 +206,7 @@ void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, * build a AVI Info Frame */ void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, - unsigned char *buffer, size_t size) + unsigned char *buffer, size_t size) { uint8_t *frame = buffer + 3; diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c index 2d71da4..d024074 100644 --- a/drivers/gpu/drm/radeon/kv_dpm.c +++ b/drivers/gpu/drm/radeon/kv_dpm.c @@ -2640,7 +2640,7 @@ static int kv_parse_power_table(struct radeon_device *rdev) struct _NonClockInfoArray *non_clock_info_array; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; u8 *power_state_offset; struct kv_ps *ps; @@ -2738,7 +2738,7 @@ int kv_dpm_init(struct radeon_device *rdev) for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) pi->at[i] = TRINITY_AT_DFLT; - pi->sram_end = SMC_RAM_END; + pi->sram_end = SMC_RAM_END; /* Enabling nb dpm on an asrock system prevents dpm from working */ if (rdev->pdev->subsystem_vendor == 0x1849) diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 158872e..b88d63c9 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -1257,7 +1257,7 @@ static void cayman_gpu_init(struct radeon_device *rdev) tmp = RREG32_CG(CG_CGTT_LOCAL_0); tmp &= ~0x00380000; WREG32_CG(CG_CGTT_LOCAL_0, tmp); - tmp = RREG32_CG(CG_CGTT_LOCAL_1); + tmp = RREG32_CG(CG_CGTT_LOCAL_1); tmp &= ~0x0e000000; WREG32_CG(CG_CGTT_LOCAL_1, tmp); } @@ -2634,7 +2634,7 @@ int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) struct atom_clock_dividers dividers; int r, i; - r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, ecclk, false, &dividers); if (r) return r; diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index c3d531a..4a601f9 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -725,9 +725,9 @@ extern int ni_mc_load_microcode(struct radeon_device *rdev); struct ni_power_info *ni_get_pi(struct radeon_device *rdev) { - struct ni_power_info *pi = rdev->pm.dpm.priv; + struct ni_power_info *pi = rdev->pm.dpm.priv; - return pi; + return pi; } struct ni_ps *ni_get_ps(struct radeon_ps *rps) @@ -1096,9 +1096,9 @@ static void ni_stop_smc(struct radeon_device *rdev) static int ni_process_firmware_header(struct radeon_device *rdev) { - struct rv7xx_power_info *pi = rv770_get_pi(rdev); - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); - struct ni_power_info *ni_pi = ni_get_pi(rdev); + struct rv7xx_power_info *pi = rv770_get_pi(rdev); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); u32 tmp; int ret; @@ -1202,14 +1202,14 @@ static int ni_enter_ulp_state(struct radeon_device *rdev) struct rv7xx_power_info *pi = rv770_get_pi(rdev); if (pi->gfx_clock_gating) { - WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); - WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); RREG32(GB_ADDR_CONFIG); - } + } WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower), - ~HOST_SMC_MSG_MASK); + ~HOST_SMC_MSG_MASK); udelay(25000); @@ -1321,12 +1321,12 @@ static void ni_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, NISLANDS_SMC_VOLTAGE_VALUE *voltage) { - struct rv7xx_power_info *pi = rv770_get_pi(rdev); + struct rv7xx_power_info *pi = rv770_get_pi(rdev); struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); if (!pi->mvdd_control) { voltage->index = eg_pi->mvdd_high_index; - voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); + voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); return; } @@ -1510,47 +1510,47 @@ int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, u32 mc_cg_config; switch (arb_freq_src) { - case MC_CG_ARB_FREQ_F0: + case MC_CG_ARB_FREQ_F0: mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; break; - case MC_CG_ARB_FREQ_F1: + case MC_CG_ARB_FREQ_F1: mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; break; - case MC_CG_ARB_FREQ_F2: + case MC_CG_ARB_FREQ_F2: mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; break; - case MC_CG_ARB_FREQ_F3: + case MC_CG_ARB_FREQ_F3: mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; break; - default: + default: return -EINVAL; } switch (arb_freq_dest) { - case MC_CG_ARB_FREQ_F0: + case MC_CG_ARB_FREQ_F0: WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); break; - case MC_CG_ARB_FREQ_F1: + case MC_CG_ARB_FREQ_F1: WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); break; - case MC_CG_ARB_FREQ_F2: + case MC_CG_ARB_FREQ_F2: WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); break; - case MC_CG_ARB_FREQ_F3: + case MC_CG_ARB_FREQ_F3: WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); @@ -1621,9 +1621,7 @@ static int ni_populate_memory_timing_parameters(struct radeon_device *rdev, (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); - radeon_atom_set_engine_dram_timings(rdev, - pl->sclk, - pl->mclk); + radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk); dram_timing = RREG32(MC_ARB_DRAM_TIMING); dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); @@ -1867,9 +1865,9 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev, mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; - if (pi->mem_gddr5) - mpll_dq_func_cntl &= ~PDNB; - mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; + if (pi->mem_gddr5) + mpll_dq_func_cntl &= ~PDNB; + mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS; mclk_pwrmgt_cntl |= (MRDCKA0_RESET | @@ -1891,15 +1889,15 @@ static int ni_populate_smc_acpi_state(struct radeon_device *rdev, MRDCKD1_PDNB); dll_cntl |= (MRDCKA0_BYPASS | - MRDCKA1_BYPASS | - MRDCKB0_BYPASS | - MRDCKB1_BYPASS | - MRDCKC0_BYPASS | - MRDCKC1_BYPASS | - MRDCKD0_BYPASS | - MRDCKD1_BYPASS); - - spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; + MRDCKA1_BYPASS | + MRDCKB0_BYPASS | + MRDCKB1_BYPASS | + MRDCKC0_BYPASS | + MRDCKC1_BYPASS | + MRDCKD0_BYPASS | + MRDCKD1_BYPASS); + + spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; spll_func_cntl_2 |= SCLK_MUX_SEL(4); table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); @@ -2089,7 +2087,7 @@ static int ni_populate_sclk_value(struct radeon_device *rdev, static int ni_init_smc_spll_table(struct radeon_device *rdev) { - struct rv7xx_power_info *pi = rv770_get_pi(rdev); + struct rv7xx_power_info *pi = rv770_get_pi(rdev); struct ni_power_info *ni_pi = ni_get_pi(rdev); SMC_NISLANDS_SPLL_DIV_TABLE *spll_table; NISLANDS_SMC_SCLK_VALUE sclk_params; @@ -2311,8 +2309,8 @@ static int ni_convert_power_level_to_smc(struct radeon_device *rdev, NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) { struct rv7xx_power_info *pi = rv770_get_pi(rdev); - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); - struct ni_power_info *ni_pi = ni_get_pi(rdev); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); int ret; bool dll_state_on; u16 std_vddc; @@ -2391,8 +2389,8 @@ static int ni_populate_smc_t(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { - struct rv7xx_power_info *pi = rv770_get_pi(rdev); - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct rv7xx_power_info *pi = rv770_get_pi(rdev); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); struct ni_ps *state = ni_get_ps(radeon_state); u32 a_t; u32 t_l, t_h; @@ -2451,8 +2449,8 @@ static int ni_populate_power_containment_values(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { - struct rv7xx_power_info *pi = rv770_get_pi(rdev); - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct rv7xx_power_info *pi = rv770_get_pi(rdev); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); struct ni_power_info *ni_pi = ni_get_pi(rdev); struct ni_ps *state = ni_get_ps(radeon_state); u32 prev_sclk; @@ -2595,7 +2593,7 @@ static int ni_enable_power_containment(struct radeon_device *rdev, struct radeon_ps *radeon_new_state, bool enable) { - struct ni_power_info *ni_pi = ni_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); PPSMC_Result smc_result; int ret = 0; @@ -2625,7 +2623,7 @@ static int ni_convert_power_state_to_smc(struct radeon_device *rdev, struct radeon_ps *radeon_state, NISLANDS_SMC_SWSTATE *smc_state) { - struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); + struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); struct ni_power_info *ni_pi = ni_get_pi(rdev); struct ni_ps *state = ni_get_ps(radeon_state); int i, ret; @@ -2770,46 +2768,46 @@ static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) bool result = true; switch (in_reg) { - case MC_SEQ_RAS_TIMING >> 2: + case MC_SEQ_RAS_TIMING >> 2: *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; break; - case MC_SEQ_CAS_TIMING >> 2: + case MC_SEQ_CAS_TIMING >> 2: *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; break; - case MC_SEQ_MISC_TIMING >> 2: + case MC_SEQ_MISC_TIMING >> 2: *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; break; - case MC_SEQ_MISC_TIMING2 >> 2: + case MC_SEQ_MISC_TIMING2 >> 2: *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; break; - case MC_SEQ_RD_CTL_D0 >> 2: + case MC_SEQ_RD_CTL_D0 >> 2: *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; break; - case MC_SEQ_RD_CTL_D1 >> 2: + case MC_SEQ_RD_CTL_D1 >> 2: *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; break; - case MC_SEQ_WR_CTL_D0 >> 2: + case MC_SEQ_WR_CTL_D0 >> 2: *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; break; - case MC_SEQ_WR_CTL_D1 >> 2: + case MC_SEQ_WR_CTL_D1 >> 2: *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; break; - case MC_PMG_CMD_EMRS >> 2: + case MC_PMG_CMD_EMRS >> 2: *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; break; - case MC_PMG_CMD_MRS >> 2: + case MC_PMG_CMD_MRS >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; break; - case MC_PMG_CMD_MRS1 >> 2: + case MC_PMG_CMD_MRS1 >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; break; - case MC_SEQ_PMG_TIMING >> 2: + case MC_SEQ_PMG_TIMING >> 2: *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; break; - case MC_PMG_CMD_MRS2 >> 2: + case MC_PMG_CMD_MRS2 >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; break; - default: + default: result = false; break; } @@ -2876,9 +2874,9 @@ static int ni_initialize_mc_reg_table(struct radeon_device *rdev) struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table; u8 module_index = rv770_get_memory_module_index(rdev); - table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); - if (!table) - return -ENOMEM; + table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); + if (!table) + return -ENOMEM; WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); @@ -2896,25 +2894,25 @@ static int ni_initialize_mc_reg_table(struct radeon_device *rdev) ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); - if (ret) - goto init_mc_done; + if (ret) + goto init_mc_done; ret = ni_copy_vbios_mc_reg_table(table, ni_table); - if (ret) - goto init_mc_done; + if (ret) + goto init_mc_done; ni_set_s0_mc_reg_index(ni_table); ret = ni_set_mc_special_registers(rdev, ni_table); - if (ret) - goto init_mc_done; + if (ret) + goto init_mc_done; ni_set_valid_flag(ni_table); init_mc_done: - kfree(table); + kfree(table); return ret; } @@ -2994,7 +2992,7 @@ static int ni_populate_mc_reg_table(struct radeon_device *rdev, { struct rv7xx_power_info *pi = rv770_get_pi(rdev); struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); - struct ni_power_info *ni_pi = ni_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; @@ -3025,7 +3023,7 @@ static int ni_upload_mc_reg_table(struct radeon_device *rdev, { struct rv7xx_power_info *pi = rv770_get_pi(rdev); struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); - struct ni_power_info *ni_pi = ni_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); struct ni_ps *ni_new_state = ni_get_ps(radeon_new_state); SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table; u16 address; @@ -3142,7 +3140,7 @@ static int ni_initialize_smc_cac_tables(struct radeon_device *rdev) struct ni_power_info *ni_pi = ni_get_pi(rdev); PP_NIslands_CACTABLES *cac_tables = NULL; int i, ret; - u32 reg; + u32 reg; if (ni_pi->enable_cac == false) return 0; @@ -3422,13 +3420,13 @@ static int ni_pcie_performance_request(struct radeon_device *rdev, struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) || - (perf_req == PCIE_PERF_REQ_PECI_GEN2)) { + (perf_req == PCIE_PERF_REQ_PECI_GEN2)) { if (eg_pi->pcie_performance_request_registered == false) radeon_acpi_pcie_notify_device_ready(rdev); eg_pi->pcie_performance_request_registered = true; return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) && - eg_pi->pcie_performance_request_registered) { + eg_pi->pcie_performance_request_registered) { eg_pi->pcie_performance_request_registered = false; return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise); } @@ -3441,12 +3439,12 @@ static int ni_advertise_gen2_capability(struct radeon_device *rdev) struct rv7xx_power_info *pi = rv770_get_pi(rdev); u32 tmp; - tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); + tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); - if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && - (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) - pi->pcie_gen2 = true; - else + if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) && + (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) + pi->pcie_gen2 = true; + else pi->pcie_gen2 = false; if (!pi->pcie_gen2) @@ -3458,8 +3456,8 @@ static int ni_advertise_gen2_capability(struct radeon_device *rdev) static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable) { - struct rv7xx_power_info *pi = rv770_get_pi(rdev); - u32 tmp, bif; + struct rv7xx_power_info *pi = rv770_get_pi(rdev); + u32 tmp, bif; tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); @@ -3502,7 +3500,7 @@ static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev, if (enable) WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); else - WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); + WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); } void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, @@ -3563,7 +3561,7 @@ void ni_update_current_ps(struct radeon_device *rdev, { struct ni_ps *new_ps = ni_get_ps(rps); struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); - struct ni_power_info *ni_pi = ni_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); eg_pi->current_rps = *rps; ni_pi->current_ps = *new_ps; @@ -3575,7 +3573,7 @@ void ni_update_requested_ps(struct radeon_device *rdev, { struct ni_ps *new_ps = ni_get_ps(rps); struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); - struct ni_power_info *ni_pi = ni_get_pi(rdev); + struct ni_power_info *ni_pi = ni_get_pi(rdev); eg_pi->requested_rps = *rps; ni_pi->requested_ps = *new_ps; @@ -3591,8 +3589,8 @@ int ni_dpm_enable(struct radeon_device *rdev) if (pi->gfx_clock_gating) ni_cg_clockgating_default(rdev); - if (btc_dpm_enabled(rdev)) - return -EINVAL; + if (btc_dpm_enabled(rdev)) + return -EINVAL; if (pi->mg_clock_gating) ni_mg_clockgating_default(rdev); if (eg_pi->ls_clock_gating) @@ -3991,7 +3989,7 @@ static int ni_parse_power_table(struct radeon_device *rdev) union pplib_clock_info *clock_info; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; struct ni_ps *ps; diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index ed12104..f86ab69 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -235,8 +235,8 @@ int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) fb_div |= 1; r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); - if (r) - return r; + if (r) + return r; /* assert PLL_RESET */ WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); @@ -1490,7 +1490,7 @@ static int r600_mc_init(struct radeon_device *rdev) rdev->fastfb_working = true; } } - } + } } radeon_update_bandwidth_info(rdev); @@ -4574,7 +4574,7 @@ uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) mutex_lock(&rdev->gpu_clock_mutex); WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); + ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); mutex_unlock(&rdev->gpu_clock_mutex); return clock; } diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 2f36fa15..b69c8de 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -1671,8 +1671,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - (idx_value & 0xfffffff0) + - ((u64)(tmp & 0xff) << 32); + (idx_value & 0xfffffff0) + + ((u64)(tmp & 0xff) << 32); ib[idx + 0] = offset; ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); @@ -1712,8 +1712,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - idx_value + - ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); + idx_value + + ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); ib[idx+0] = offset; ib[idx+1] = upper_32_bits(offset) & 0xff; @@ -1764,8 +1764,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); ib[idx+2] = upper_32_bits(offset) & 0xff; @@ -1876,8 +1876,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } offset = reloc->gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = offset & 0xfffffff8; ib[idx+2] = upper_32_bits(offset) & 0xff; @@ -1898,8 +1898,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, } offset = reloc->gpu_offset + - (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + - ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); + (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + + ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); ib[idx+1] = offset & 0xfffffffc; ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c index fa21544..6a4b020 100644 --- a/drivers/gpu/drm/radeon/r600_dpm.c +++ b/drivers/gpu/drm/radeon/r600_dpm.c @@ -844,7 +844,7 @@ int r600_get_platform_caps(struct radeon_device *rdev) struct radeon_mode_info *mode_info = &rdev->mode_info; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; if (!atom_parse_data_header(mode_info->atom_context, index, NULL, @@ -874,7 +874,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) union fan_info *fan_info; ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; int ret, i; @@ -1070,7 +1070,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) ext_hdr->usVCETableOffset) { VCEClockInfoArray *array = (VCEClockInfoArray *) (mode_info->atom_context->bios + data_offset + - le16_to_cpu(ext_hdr->usVCETableOffset) + 1); + le16_to_cpu(ext_hdr->usVCETableOffset) + 1); ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *) (mode_info->atom_context->bios + data_offset + diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index e85894a..e82a99c 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -215,7 +215,7 @@ void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, * build a HDMI Video Info Frame */ void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, - unsigned char *buffer, size_t size) + unsigned char *buffer, size_t size) { uint8_t *frame = buffer + 3; @@ -312,7 +312,7 @@ void r600_hdmi_audio_workaround(struct drm_encoder *encoder) } void r600_hdmi_audio_set_dto(struct radeon_device *rdev, - struct radeon_crtc *crtc, unsigned int clock) + struct radeon_crtc *crtc, unsigned int clock) { struct radeon_encoder *radeon_encoder; struct radeon_encoder_atom_dig *dig; diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index de9a2ff..f8097a0 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -2095,7 +2095,7 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) struct radeon_i2c_bus_rec i2c_bus; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; if (!atom_parse_data_header(mode_info->atom_context, index, NULL, @@ -2575,7 +2575,7 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) bool valid; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; if (!atom_parse_data_header(mode_info->atom_context, index, NULL, @@ -2666,7 +2666,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) bool valid; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; u8 *power_state_offset; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 4de23ae..ec8de1a 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1161,9 +1161,9 @@ static void radeon_check_arguments(struct radeon_device *rdev) radeon_vm_size = 4; } - /* - * Max GPUVM size for Cayman, SI and CI are 40 bits. - */ + /* + * Max GPUVM size for Cayman, SI and CI are 40 bits. + */ if (radeon_vm_size > 1024) { dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", radeon_vm_size); @@ -1902,7 +1902,7 @@ int radeon_debugfs_add_files(struct radeon_device *rdev, if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { DRM_ERROR("Reached maximum number of debugfs components.\n"); DRM_ERROR("Report so we increase " - "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); + "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); return -EINVAL; } rdev->debugfs[rdev->debugfs_count].files = files; diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index a4674bf..150b220 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -406,7 +406,7 @@ static void radeon_flip_work_func(struct work_struct *__work) int vpos, hpos, stat, min_udelay; struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; - down_read(&rdev->exclusive_lock); + down_read(&rdev->exclusive_lock); if (work->fence) { struct radeon_fence *fence; @@ -906,7 +906,7 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den, *den /= tmp; /* make sure nominator is large enough */ - if (*nom < nom_min) { + if (*nom < nom_min) { tmp = DIV_ROUND_UP(nom_min, *nom); *nom *= tmp; *den *= tmp; @@ -946,7 +946,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); /* limit fb divider to its maximum */ - if (*fb_div > fb_div_max) { + if (*fb_div > fb_div_max) { *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); *fb_div = fb_div_max; } diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index d2e628e..4b2c72d 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -38,9 +38,9 @@ #include <linux/vga_switcheroo.h> /* object hierarchy - - this contains a helper + a radeon fb - the helper contains a pointer to radeon framebuffer baseclass. -*/ + * this contains a helper + a radeon fb + * the helper contains a pointer to radeon framebuffer baseclass. + */ struct radeon_fbdev { struct drm_fb_helper helper; struct radeon_framebuffer rfb; diff --git a/drivers/gpu/drm/radeon/radeon_ib.c b/drivers/gpu/drm/radeon/radeon_ib.c index c39ce1f..92ce0e5 100644 --- a/drivers/gpu/drm/radeon/radeon_ib.c +++ b/drivers/gpu/drm/radeon/radeon_ib.c @@ -274,7 +274,7 @@ int radeon_ib_ring_tests(struct radeon_device *rdev) if (i == RADEON_RING_TYPE_GFX_INDEX) { /* oh, oh, that's really bad */ DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); - rdev->accel_working = false; + rdev->accel_working = false; return r; } else { @@ -304,7 +304,7 @@ static int radeon_debugfs_sa_info(struct seq_file *m, void *data) } static struct drm_info_list radeon_debugfs_sa_list[] = { - {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, + {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, }; #endif diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 88dc973..868c3ba 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -818,52 +818,52 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & ~(RADEON_TMDS_TRANSMITTER_PLLRST); - if (rdev->family == CHIP_R200 || - rdev->family == CHIP_R100 || - ASIC_IS_R300(rdev)) - tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); - else /* RV chips got this bit reversed */ - tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; - - fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | - (RADEON_FP_CRTC_DONT_SHADOW_VPAR | - RADEON_FP_CRTC_DONT_SHADOW_HEND)); - - fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); - - fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | - RADEON_FP_DFP_SYNC_SEL | - RADEON_FP_CRT_SYNC_SEL | - RADEON_FP_CRTC_LOCK_8DOT | - RADEON_FP_USE_SHADOW_EN | - RADEON_FP_CRTC_USE_SHADOW_VEND | - RADEON_FP_CRT_SYNC_ALT); - - if (1) /* FIXME rgbBits == 8 */ - fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ - else - fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ - - if (radeon_crtc->crtc_id == 0) { - if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { - fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; - if (radeon_encoder->rmx_type != RMX_OFF) - fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; - else - fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; - } else - fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; - } else { - if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { - fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; - fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; - } else - fp_gen_cntl |= RADEON_FP_SEL_CRTC2; - } - - WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); - WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); - WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); + if (rdev->family == CHIP_R200 || + rdev->family == CHIP_R100 || + ASIC_IS_R300(rdev)) + tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); + else /* RV chips got this bit reversed */ + tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; + + fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | + (RADEON_FP_CRTC_DONT_SHADOW_VPAR | + RADEON_FP_CRTC_DONT_SHADOW_HEND)); + + fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); + + fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | + RADEON_FP_DFP_SYNC_SEL | + RADEON_FP_CRT_SYNC_SEL | + RADEON_FP_CRTC_LOCK_8DOT | + RADEON_FP_USE_SHADOW_EN | + RADEON_FP_CRTC_USE_SHADOW_VEND | + RADEON_FP_CRT_SYNC_ALT); + + if (1) /* FIXME rgbBits == 8 */ + fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ + else + fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ + + if (radeon_crtc->crtc_id == 0) { + if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { + fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; + if (radeon_encoder->rmx_type != RMX_OFF) + fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; + else + fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; + } else + fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; + } else { + if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { + fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; + fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; + } else + fp_gen_cntl |= RADEON_FP_SEL_CRTC2; + } + + WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); + WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); + WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); if (rdev->is_atom_bios) radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index fb6ad14..dd46c38 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -214,8 +214,8 @@ int radeon_bo_create(struct radeon_device *rdev, INIT_LIST_HEAD(&bo->list); INIT_LIST_HEAD(&bo->va); bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | - RADEON_GEM_DOMAIN_GTT | - RADEON_GEM_DOMAIN_CPU); + RADEON_GEM_DOMAIN_GTT | + RADEON_GEM_DOMAIN_CPU); bo->flags = flags; /* PCI GART is always snooped */ @@ -848,7 +848,7 @@ int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) * */ void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, - bool shared) + bool shared) { struct reservation_object *resv = bo->tbo.resv; diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 460c8f2..3748a62 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -79,7 +79,7 @@ void radeon_pm_acpi_event_handler(struct radeon_device *rdev) radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); } mutex_unlock(&rdev->pm.mutex); - } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { + } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { if (rdev->pm.profile == PM_PROFILE_AUTO) { mutex_lock(&rdev->pm.mutex); radeon_pm_update_profile(rdev); diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c index e6ad54c..b0eb28e 100644 --- a/drivers/gpu/drm/radeon/radeon_semaphore.c +++ b/drivers/gpu/drm/radeon/radeon_semaphore.c @@ -56,7 +56,7 @@ int radeon_semaphore_create(struct radeon_device *rdev, } bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ridx, - struct radeon_semaphore *semaphore) + struct radeon_semaphore *semaphore) { struct radeon_ring *ring = &rdev->ring[ridx]; @@ -73,7 +73,7 @@ bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ridx, } bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ridx, - struct radeon_semaphore *semaphore) + struct radeon_semaphore *semaphore) { struct radeon_ring *ring = &rdev->ring[ridx]; diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 6edcb54..6fe9e4e 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c @@ -722,9 +722,11 @@ static int radeon_uvd_send_msg(struct radeon_device *rdev, return r; } -/* multiple fence commands without any stream commands in between can - crash the vcpu so just try to emmit a dummy create/destroy msg to - avoid this */ +/* + * multiple fence commands without any stream commands in between can + * crash the vcpu so just try to emmit a dummy create/destroy msg to + * avoid this + */ int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, uint32_t handle, struct radeon_fence **fence) { diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index 566a1a0..c1c619f 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -166,7 +166,7 @@ int radeon_vce_init(struct radeon_device *rdev) for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { atomic_set(&rdev->vce.handles[i], 0); rdev->vce.filp[i] = NULL; - } + } return 0; } @@ -389,7 +389,7 @@ int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, r = radeon_ib_schedule(rdev, &ib, NULL, false); if (r) { - DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); + DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); } if (fence) @@ -446,7 +446,7 @@ int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, r = radeon_ib_schedule(rdev, &ib, NULL, false); if (r) { - DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); + DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); } if (fence) @@ -769,18 +769,18 @@ int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) radeon_ring_unlock_commit(rdev, ring, false); for (i = 0; i < rdev->usec_timeout; i++) { - if (vce_v1_0_get_rptr(rdev, ring) != rptr) - break; - DRM_UDELAY(1); + if (vce_v1_0_get_rptr(rdev, ring) != rptr) + break; + DRM_UDELAY(1); } if (i < rdev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", - ring->idx, i); + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); } else { - DRM_ERROR("radeon: ring %d test failed\n", - ring->idx); - r = -ETIMEDOUT; + DRM_ERROR("radeon: ring %d test failed\n", + ring->idx); + r = -ETIMEDOUT; } return r; diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index 3979632..a135874 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c @@ -611,15 +611,16 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr) */ static uint32_t radeon_vm_page_flags(uint32_t flags) { - uint32_t hw_flags = 0; - hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0; - hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; - hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; - if (flags & RADEON_VM_PAGE_SYSTEM) { - hw_flags |= R600_PTE_SYSTEM; - hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; - } - return hw_flags; + uint32_t hw_flags = 0; + + hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0; + hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0; + hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0; + if (flags & RADEON_VM_PAGE_SYSTEM) { + hw_flags |= R600_PTE_SYSTEM; + hw_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0; + } + return hw_flags; } /** diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c index cb0afe7..94b48fc 100644 --- a/drivers/gpu/drm/radeon/rs780_dpm.c +++ b/drivers/gpu/drm/radeon/rs780_dpm.c @@ -795,7 +795,7 @@ static int rs780_parse_power_table(struct radeon_device *rdev) union pplib_clock_info *clock_info; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; struct igp_ps *ps; diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c index 97e5a6f..25e2930 100644 --- a/drivers/gpu/drm/radeon/rv6xx_dpm.c +++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c @@ -209,7 +209,7 @@ static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev static bool rv6xx_can_step_post_div(struct radeon_device *rdev, struct rv6xx_sclk_stepping *cur, - struct rv6xx_sclk_stepping *target) + struct rv6xx_sclk_stepping *target) { return (cur->post_divider > target->post_divider) && ((cur->vco_frequency * target->post_divider) <= @@ -239,7 +239,7 @@ static bool rv6xx_reached_stepping_target(struct radeon_device *rdev, static void rv6xx_generate_steps(struct radeon_device *rdev, u32 low, u32 high, - u32 start_index, u8 *end_index) + u32 start_index, u8 *end_index) { struct rv6xx_sclk_stepping cur; struct rv6xx_sclk_stepping target; @@ -1356,23 +1356,23 @@ static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) enum radeon_dpm_event_src dpm_event_src; switch (sources) { - case 0: - default: + case 0: + default: want_thermal_protection = false; break; - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): want_thermal_protection = true; dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; break; - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): want_thermal_protection = true; dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; break; - case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | + case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): - want_thermal_protection = true; + want_thermal_protection = true; dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; break; } @@ -1879,7 +1879,7 @@ static int rv6xx_parse_power_table(struct radeon_device *rdev) union pplib_clock_info *clock_info; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; struct rv6xx_ps *ps; diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c b/drivers/gpu/drm/radeon/rv740_dpm.c index c4c8da5..4b85082 100644 --- a/drivers/gpu/drm/radeon/rv740_dpm.c +++ b/drivers/gpu/drm/radeon/rv740_dpm.c @@ -36,28 +36,28 @@ u32 rv740_get_decoded_reference_divider(u32 encoded_ref) u32 ref = 0; switch (encoded_ref) { - case 0: + case 0: ref = 1; break; - case 16: + case 16: ref = 2; break; - case 17: + case 17: ref = 3; break; - case 18: + case 18: ref = 2; break; - case 19: + case 19: ref = 3; break; - case 20: + case 20: ref = 4; break; - case 21: + case 21: ref = 5; break; - default: + default: DRM_ERROR("Invalid encoded Reference Divider\n"); ref = 0; break; diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c index e830c89..a010dec 100644 --- a/drivers/gpu/drm/radeon/rv770_dpm.c +++ b/drivers/gpu/drm/radeon/rv770_dpm.c @@ -345,27 +345,27 @@ static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) int ret = 0; switch (postdiv) { - case 1: + case 1: *encoded_postdiv = 0; break; - case 2: + case 2: *encoded_postdiv = 1; break; - case 4: + case 4: *encoded_postdiv = 2; break; - case 8: + case 8: *encoded_postdiv = 3; break; - case 16: + case 16: *encoded_postdiv = 4; break; - default: + default: ret = -EINVAL; break; } - return ret; + return ret; } u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf) @@ -1175,15 +1175,15 @@ static int rv770_init_smc_table(struct radeon_device *rdev, rv770_populate_smc_mvdd_table(rdev, table); switch (rdev->pm.int_thermal_type) { - case THERMAL_TYPE_RV770: - case THERMAL_TYPE_ADT7473_WITH_INTERNAL: + case THERMAL_TYPE_RV770: + case THERMAL_TYPE_ADT7473_WITH_INTERNAL: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; break; - case THERMAL_TYPE_NONE: + case THERMAL_TYPE_NONE: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; break; - case THERMAL_TYPE_EXTERNAL_GPIO: - default: + case THERMAL_TYPE_EXTERNAL_GPIO: + default: table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; break; } @@ -1567,18 +1567,18 @@ void rv770_reset_smio_status(struct radeon_device *rdev) sw_smio_index = (RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT; switch (sw_smio_index) { - case 3: + case 3: vid_smio_cntl = RREG32(S3_VID_LOWER_SMIO_CNTL); break; - case 2: + case 2: vid_smio_cntl = RREG32(S2_VID_LOWER_SMIO_CNTL); break; - case 1: + case 1: vid_smio_cntl = RREG32(S1_VID_LOWER_SMIO_CNTL); break; - case 0: + case 0: return; - default: + default: vid_smio_cntl = pi->s0_vid_lower_smio_cntl; break; } @@ -1817,21 +1817,21 @@ static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) enum radeon_dpm_event_src dpm_event_src; switch (sources) { - case 0: - default: + case 0: + default: want_thermal_protection = false; break; - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): want_thermal_protection = true; dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; break; - case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): + case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): want_thermal_protection = true; dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; break; - case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | + case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): want_thermal_protection = true; dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; @@ -2273,7 +2273,7 @@ int rv7xx_parse_power_table(struct radeon_device *rdev) union pplib_clock_info *clock_info; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; struct rv7xx_ps *ps; diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index f878d69..e894be2 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -1307,7 +1307,7 @@ int si_get_allowed_info_register(struct radeon_device *rdev, */ u32 si_get_xclk(struct radeon_device *rdev) { - u32 reference_clock = rdev->clock.spll.reference_freq; + u32 reference_clock = rdev->clock.spll.reference_freq; u32 tmp; tmp = RREG32(CG_CLKPIN_CNTL_2); @@ -7314,7 +7314,7 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev) mutex_lock(&rdev->gpu_clock_mutex); WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | - ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); + ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); mutex_unlock(&rdev->gpu_clock_mutex); return clock; } @@ -7775,33 +7775,33 @@ static void si_program_aspm(struct radeon_device *rdev) int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev) { - unsigned i; + unsigned i; - /* make sure VCEPLL_CTLREQ is deasserted */ - WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + /* make sure VCEPLL_CTLREQ is deasserted */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); - mdelay(10); + mdelay(10); - /* assert UPLL_CTLREQ */ - WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + /* assert UPLL_CTLREQ */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); - /* wait for CTLACK and CTLACK2 to get asserted */ - for (i = 0; i < 100; ++i) { - uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; - if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) - break; - mdelay(10); - } + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } - /* deassert UPLL_CTLREQ */ - WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + /* deassert UPLL_CTLREQ */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); - if (i == 100) { - DRM_ERROR("Timeout setting UVD clocks!\n"); - return -ETIMEDOUT; - } + if (i == 100) { + DRM_ERROR("Timeout setting UVD clocks!\n"); + return -ETIMEDOUT; + } - return 0; + return 0; } int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index a82b891..cb75ab7 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -499,7 +499,7 @@ static const struct si_cac_config_reg lcac_pitcairn[] = static const struct si_cac_config_reg cac_override_pitcairn[] = { - { 0xFFFFFFFF } + { 0xFFFFFFFF } }; static const struct si_powertune_data powertune_data_pitcairn = @@ -991,7 +991,7 @@ static const struct si_cac_config_reg lcac_cape_verde[] = static const struct si_cac_config_reg cac_override_cape_verde[] = { - { 0xFFFFFFFF } + { 0xFFFFFFFF } }; static const struct si_powertune_data powertune_data_cape_verde = @@ -1762,9 +1762,9 @@ static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); static struct si_power_info *si_get_pi(struct radeon_device *rdev) { - struct si_power_info *pi = rdev->pm.dpm.priv; + struct si_power_info *pi = rdev->pm.dpm.priv; - return pi; + return pi; } static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, @@ -3150,9 +3150,9 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, } } - for (i = 0; i < ps->performance_level_count; i++) - btc_adjust_clock_combinations(rdev, max_limits, - &ps->performance_levels[i]); + for (i = 0; i < ps->performance_level_count; i++) + btc_adjust_clock_combinations(rdev, max_limits, + &ps->performance_levels[i]); for (i = 0; i < ps->performance_level_count; i++) { if (ps->performance_levels[i].vddc < min_vce_voltage) @@ -3291,7 +3291,7 @@ static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) case 0: default: want_thermal_protection = false; - break; + break; case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): want_thermal_protection = true; dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; @@ -3493,7 +3493,7 @@ static int si_process_firmware_header(struct radeon_device *rdev) if (ret) return ret; - si_pi->state_table_start = tmp; + si_pi->state_table_start = tmp; ret = si_read_smc_sram_dword(rdev, SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + @@ -3652,7 +3652,7 @@ static void si_program_response_times(struct radeon_device *rdev) si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; - backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; + backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; if (voltage_response_time == 0) voltage_response_time = 1000; @@ -3760,7 +3760,7 @@ static void si_setup_bsp(struct radeon_device *rdev) &pi->pbsu); - pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); + pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); WREG32(CG_BSP, pi->dsp); @@ -4308,7 +4308,7 @@ static int si_populate_memory_timing_parameters(struct radeon_device *rdev, radeon_atom_set_engine_dram_timings(rdev, pl->sclk, - pl->mclk); + pl->mclk); dram_timing = RREG32(MC_ARB_DRAM_TIMING); dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); @@ -4343,7 +4343,7 @@ static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, si_pi->sram_end); if (ret) break; - } + } return ret; } @@ -4821,9 +4821,9 @@ static int si_calculate_sclk_params(struct radeon_device *rdev, spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; spll_func_cntl_2 |= SCLK_MUX_SEL(2); - spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; - spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); - spll_func_cntl_3 |= SPLL_DITHEN; + spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; + spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); + spll_func_cntl_3 |= SPLL_DITHEN; if (pi->sclk_ss) { struct radeon_atom_ss ss; @@ -4930,15 +4930,15 @@ static int si_populate_mclk_value(struct radeon_device *rdev, tmp = freq_nom / reference_clock; tmp = tmp * tmp; if (radeon_atombios_get_asic_ss_info(rdev, &ss, - ASIC_INTERNAL_MEMORY_SS, freq_nom)) { + ASIC_INTERNAL_MEMORY_SS, freq_nom)) { u32 clks = reference_clock * 5 / ss.rate; u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); - mpll_ss1 &= ~CLKV_MASK; - mpll_ss1 |= CLKV(clkv); + mpll_ss1 &= ~CLKV_MASK; + mpll_ss1 |= CLKV(clkv); - mpll_ss2 &= ~CLKS_MASK; - mpll_ss2 |= CLKS(clks); + mpll_ss2 &= ~CLKS_MASK; + mpll_ss2 |= CLKS(clks); } } @@ -5265,7 +5265,7 @@ static int si_convert_power_state_to_smc(struct radeon_device *rdev, ni_pi->enable_power_containment = false; ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); - if (ret) + if (ret) ni_pi->enable_sq_ramping = false; return si_populate_smc_t(rdev, radeon_state, smc_state); @@ -5436,46 +5436,46 @@ static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) case MC_SEQ_RAS_TIMING >> 2: *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; break; - case MC_SEQ_CAS_TIMING >> 2: + case MC_SEQ_CAS_TIMING >> 2: *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; break; - case MC_SEQ_MISC_TIMING >> 2: + case MC_SEQ_MISC_TIMING >> 2: *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; break; - case MC_SEQ_MISC_TIMING2 >> 2: + case MC_SEQ_MISC_TIMING2 >> 2: *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; break; - case MC_SEQ_RD_CTL_D0 >> 2: + case MC_SEQ_RD_CTL_D0 >> 2: *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; break; - case MC_SEQ_RD_CTL_D1 >> 2: + case MC_SEQ_RD_CTL_D1 >> 2: *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; break; - case MC_SEQ_WR_CTL_D0 >> 2: + case MC_SEQ_WR_CTL_D0 >> 2: *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; break; - case MC_SEQ_WR_CTL_D1 >> 2: + case MC_SEQ_WR_CTL_D1 >> 2: *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; break; - case MC_PMG_CMD_EMRS >> 2: + case MC_PMG_CMD_EMRS >> 2: *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; break; - case MC_PMG_CMD_MRS >> 2: + case MC_PMG_CMD_MRS >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; break; - case MC_PMG_CMD_MRS1 >> 2: + case MC_PMG_CMD_MRS1 >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; break; - case MC_SEQ_PMG_TIMING >> 2: + case MC_SEQ_PMG_TIMING >> 2: *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; break; - case MC_PMG_CMD_MRS2 >> 2: + case MC_PMG_CMD_MRS2 >> 2: *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; break; - case MC_SEQ_WR_CTL_2 >> 2: + case MC_SEQ_WR_CTL_2 >> 2: *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; break; - default: + default: result = false; break; } @@ -5562,19 +5562,19 @@ static int si_initialize_mc_reg_table(struct radeon_device *rdev) WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); - ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); - if (ret) - goto init_mc_done; + ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); + if (ret) + goto init_mc_done; - ret = si_copy_vbios_mc_reg_table(table, si_table); - if (ret) - goto init_mc_done; + ret = si_copy_vbios_mc_reg_table(table, si_table); + if (ret) + goto init_mc_done; si_set_s0_mc_reg_index(si_table); ret = si_set_mc_special_registers(rdev, si_table); - if (ret) - goto init_mc_done; + if (ret) + goto init_mc_done; si_set_valid_flag(si_table); @@ -5715,10 +5715,10 @@ static int si_upload_mc_reg_table(struct radeon_device *rdev, static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) { - if (enable) - WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); - else - WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); + if (enable) + WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); + else + WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); } static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, @@ -6820,7 +6820,7 @@ static int si_parse_power_table(struct radeon_device *rdev) struct _NonClockInfoArray *non_clock_info_array; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; u8 *power_state_offset; struct ni_ps *ps; diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index cd08628..f0d5c17 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -787,8 +787,8 @@ static void sumo_program_acpi_power_level(struct radeon_device *rdev) struct atom_clock_dividers dividers; int ret; - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, - pi->acpi_pl.sclk, + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + pi->acpi_pl.sclk, false, &dividers); if (ret) return; @@ -1462,7 +1462,7 @@ static int sumo_parse_power_table(struct radeon_device *rdev) struct _NonClockInfoArray *non_clock_info_array; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; u8 *power_state_offset; struct sumo_ps *ps; diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index d34bfcda..6730367 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -369,8 +369,8 @@ static void trinity_gfx_powergating_initialize(struct radeon_device *rdev) int ret; u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, - 25000, false, &dividers); + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + 25000, false, &dividers); if (ret) return; @@ -587,8 +587,8 @@ static void trinity_set_divider_value(struct radeon_device *rdev, u32 value; u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, - sclk, false, &dividers); + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + sclk, false, &dividers); if (ret) return; @@ -597,8 +597,8 @@ static void trinity_set_divider_value(struct radeon_device *rdev, value |= CLK_DIVIDER(dividers.post_div); WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); - ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, - sclk/2, false, &dividers); + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + sclk/2, false, &dividers); if (ret) return; @@ -1045,14 +1045,14 @@ static int trinity_set_thermal_temperature_range(struct radeon_device *rdev, int low_temp = 0 * 1000; int high_temp = 255 * 1000; - if (low_temp < min_temp) + if (low_temp < min_temp) low_temp = min_temp; - if (high_temp > max_temp) + if (high_temp > max_temp) high_temp = max_temp; - if (high_temp < low_temp) { + if (high_temp < low_temp) { DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); - return -EINVAL; - } + return -EINVAL; + } WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); @@ -1737,7 +1737,7 @@ static int trinity_parse_power_table(struct radeon_device *rdev) struct _NonClockInfoArray *non_clock_info_array; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); - u16 data_offset; + u16 data_offset; u8 frev, crev; u8 *power_state_offset; struct sumo_ps *ps; diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c index cdeaab7..fce2144 100644 --- a/drivers/gpu/drm/radeon/vce_v2_0.c +++ b/drivers/gpu/drm/radeon/vce_v2_0.c @@ -53,7 +53,7 @@ static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); WREG32(VCE_CGTT_CLK_OVERRIDE, 0); - } else { + } else { tmp = RREG32(VCE_CLOCK_GATING_B); tmp |= 0xe7; tmp &= ~0xe70000;

[1/3] drm/radeon: fix indentation.

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