From patchwork Wed Mar 23 13:25:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 8650051 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C328DC0553 for ; Wed, 23 Mar 2016 13:26:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F1861203DB for ; Wed, 23 Mar 2016 13:26:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3D1BD203AB for ; Wed, 23 Mar 2016 13:26:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DAD96E865; Wed, 23 Mar 2016 13:26:20 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97A626E864 for ; Wed, 23 Mar 2016 13:26:17 +0000 (UTC) Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4H00C35UNQNNA0@mailout1.w1.samsung.com> for dri-devel@lists.freedesktop.org; Wed, 23 Mar 2016 13:26:14 +0000 (GMT) X-AuditID: cbfec7f4-f796c6d000001486-e1-56f29976c683 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 05.9E.05254.67992F65; Wed, 23 Mar 2016 13:26:14 +0000 (GMT) Received: from amdc1061.digital.local ([106.116.147.88]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4H0086MUNPPA00@eusync4.samsung.com>; Wed, 23 Mar 2016 13:26:14 +0000 (GMT) From: Andrzej Hajda To: Inki Dae Subject: [PATCH 2/6] drm/exynos: add support for pipeline clock to the framework Date: Wed, 23 Mar 2016 14:25:58 +0100 Message-id: <1458739562-32327-3-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1458739562-32327-1-git-send-email-a.hajda@samsung.com> References: <1458739562-32327-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmluLIzCtJLcpLzFFi42I5/e/4Nd2ymZ/CDNY+M7K4te4cq8XGGetZ La58fc9mMen+BBaLs01v2C1mnN/HZLH2yF12B3aP+93HmTz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4+/fgywFn/gqLmz5ytTAuJini5GTQ0LAROLk5vNMELaYxIV769m6GLk4hASWMkoc vP+KCcJpYpK4vnwTI0gVm4CmxN/NN9lAbBEBZYlV+9rZQYqYBe4xSXy78BQsISwQIHF7/Qyw sSwCqhKPp31gBbF5BZwlvrc8Z4ZYJydx8thksDingIvEtAs9YL1CQDXrJy9mnsDIu4CRYRWj aGppckFxUnquoV5xYm5xaV66XnJ+7iZGSBB92cG4+JjVIUYBDkYlHl6JMx/DhFgTy4orcw8x SnAwK4nwSk79FCbEm5JYWZValB9fVJqTWnyIUZqDRUmcd+6u9yFCAumJJanZqakFqUUwWSYO TqkGxgkf6tyPZH8N+fv+lmZznPy0sHOi4Y5PPCV4M1w/im1oLXOz/K0fnX5lAZupiZZ3u6jx wwvJtf128ckfSqecbs8O0Yh+mVP1wubu3nNXP0jxP/5S5OBxNvt0wDeNQ+rrDjut+7e5dl5F s9AD7/+hTStqp3/fJ9bqrTZ7vvs5l8OtGW//rl24SYmlOCPRUIu5qDgRAJnPtOgeAgAA Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , "open list:DRM DRIVERS FOR EXYNOS" , Andrzej Hajda , Kyungmin Park , Marek Szyprowski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Components belonging to the same pipeline often requires synchronized clocks. Such clocks are sometimes provided by external clock controller, but they can be also provided by pipeline components. In latter case there should be a way to access them from another component belonging to the same pipeline. This is the case of: - DECON,FIMD -> HDMI and HDMI-PHY clock, - FIMD -> DP and DP clock in FIMD. The latter case has been solved by clock_enable callback in exynos_drm_crtc_ops. This solutin will not work with HDMI path as in this case clock is provided by encoder. This patch provides more generic solution allowing to register pipeline clock during initialization in exynos_drm_crtc structure. This way the clock will be easily accessible from both components. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_drm_drv.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index fcea940..6ee0b20 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -154,6 +154,10 @@ struct exynos_drm_crtc_ops { void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable); }; +struct exynos_drm_clk { + void (*enable)(struct exynos_drm_clk *clk, bool enable); +}; + /* * Exynos specific crtc structure. * @@ -182,8 +186,16 @@ struct exynos_drm_crtc { atomic_t pending_update; const struct exynos_drm_crtc_ops *ops; void *ctx; + struct exynos_drm_clk *pipe_clk; }; +static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc, + bool enable) +{ + if (crtc->pipe_clk) + crtc->pipe_clk->enable(crtc->pipe_clk, enable); +} + struct exynos_drm_g2d_private { struct device *dev; struct list_head inuse_cmdlist;