From patchwork Wed Mar 23 13:25:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 8650091 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9CBD09FB32 for ; Wed, 23 Mar 2016 13:26:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A3AAD2039E for ; Wed, 23 Mar 2016 13:26:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 80D8E203E5 for ; Wed, 23 Mar 2016 13:26:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A238E6E86C; Wed, 23 Mar 2016 13:26:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout3.w1.samsung.com (mailout3.w1.samsung.com [210.118.77.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 211086E85C for ; Wed, 23 Mar 2016 13:26:19 +0000 (UTC) Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4H00238UNRCGA0@mailout3.w1.samsung.com> for dri-devel@lists.freedesktop.org; Wed, 23 Mar 2016 13:26:15 +0000 (GMT) X-AuditID: cbfec7f5-f792a6d000001302-79-56f29977f221 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 4C.2B.04866.77992F65; Wed, 23 Mar 2016 13:26:15 +0000 (GMT) Received: from amdc1061.digital.local ([106.116.147.88]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4H0086MUNPPA00@eusync4.samsung.com>; Wed, 23 Mar 2016 13:26:15 +0000 (GMT) From: Andrzej Hajda To: Inki Dae Subject: [PATCH 3/6] drm/exynos/hdmi: expose HDMI-PHY clock as pipeline clock Date: Wed, 23 Mar 2016 14:25:59 +0100 Message-id: <1458739562-32327-4-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1458739562-32327-1-git-send-email-a.hajda@samsung.com> References: <1458739562-32327-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupiluLIzCtJLcpLzFFi42I5/e/4Nd3ymZ/CDFp/8ljcWneO1WLjjPWs Fle+vmezmHR/AovF2aY37BYzzu9jslh75C67A7vH/e7jTB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CV0XvgPkvBTfmKNx8WMzUw3pfqYuTkkBAwkTj0+gMrhC0mceHeerYuRi4OIYGljBJb Lt5hgXCamCQ+954Dq2IT0JT4u/kmG4gtIqAssWpfOztIEbPAPSaJbxeegiWEBXwlDjUfBLNZ BFQlHt+azNTFyMHBK+AsMfMpM8Q2OYmTxyaDzeQUcJGYdqEHrFwIqGT95MXMExh5FzAyrGIU TS1NLihOSs810itOzC0uzUvXS87P3cQICaGvOxiXHrM6xCjAwajEw1tw7mOYEGtiWXFl7iFG CQ5mJRFeyamfwoR4UxIrq1KL8uOLSnNSiw8xSnOwKInzztz1PkRIID2xJDU7NbUgtQgmy8TB KdXAeCBe0/w+s+E99vtrAps0556R+9YnY52/xd35XuJSs7vHStb1NzBIuz1fPT1YX9S656ug bXBjUrZcp73k7TcLsmL5OMI3C7z/PSmvLaRUdbEpO8v6+3HSRy3OnnaZJfg+qNugW5ExTfxy onvTjsnffbt3hNycYFrPXMESkdr8b8GpSXNeXi1QYinOSDTUYi4qTgQA6UA8nR0CAAA= Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , "open list:DRM DRIVERS FOR EXYNOS" , Andrzej Hajda , Kyungmin Park , Marek Szyprowski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP HDMI-PHY clock should be accessible from other components in the pipeline. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_hdmi.c | 67 ++++++++++++++++++++++++++---------- 1 file changed, 48 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 49a5902..0d1c2f0 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -146,6 +146,7 @@ struct hdmi_context { struct clk **clk_muxes; struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)]; struct regulator *reg_hdmi_en; + struct exynos_drm_clk phy_clk; }; static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) @@ -1448,7 +1449,6 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) static void hdmi_conf_apply(struct hdmi_context *hdata) { - hdmiphy_conf_apply(hdata); hdmi_start(hdata, false); hdmi_conf_init(hdata); hdmi_audio_init(hdata); @@ -1481,10 +1481,8 @@ static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0); } -static void hdmi_enable(struct drm_encoder *encoder) +static void hdmiphy_enable(struct hdmi_context *hdata) { - struct hdmi_context *hdata = encoder_to_hdmi(encoder); - if (hdata->powered) return; @@ -1500,11 +1498,40 @@ static void hdmi_enable(struct drm_encoder *encoder) hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN); - hdmi_conf_apply(hdata); + hdmiphy_conf_apply(hdata); hdata->powered = true; } +static void hdmiphy_disable(struct hdmi_context *hdata) +{ + if (!hdata->powered) + return; + + hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); + + hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN); + + hdmi_set_refclk(hdata, false); + + regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, + PMU_HDMI_PHY_ENABLE_BIT, 0); + + regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk); + + pm_runtime_put_sync(hdata->dev); + + hdata->powered = false; +} + +static void hdmi_enable(struct drm_encoder *encoder) +{ + struct hdmi_context *hdata = encoder_to_hdmi(encoder); + + hdmiphy_enable(hdata); + hdmi_conf_apply(hdata); +} + static void hdmi_disable(struct drm_encoder *encoder) { struct hdmi_context *hdata = encoder_to_hdmi(encoder); @@ -1528,22 +1555,9 @@ static void hdmi_disable(struct drm_encoder *encoder) if (funcs && funcs->disable) (*funcs->disable)(crtc); - hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); - cancel_delayed_work(&hdata->hotplug_work); - hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN); - - hdmi_set_refclk(hdata, false); - - regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, - PMU_HDMI_PHY_ENABLE_BIT, 0); - - regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk); - - pm_runtime_put_sync(hdata->dev); - - hdata->powered = false; + hdmiphy_disable(hdata); } static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = { @@ -1627,6 +1641,17 @@ static int hdmi_clk_init(struct hdmi_context *hdata) return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes); } +static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable) +{ + struct hdmi_context *hdata = container_of(clk, struct hdmi_context, + phy_clk); + + if (enable) + hdmiphy_enable(hdata); + else + hdmiphy_disable(hdata); +} + static int hdmi_resources_init(struct hdmi_context *hdata) { struct device *dev = hdata->dev; @@ -1710,6 +1735,10 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data) if (pipe < 0) return pipe; + hdata->phy_clk.enable = hdmiphy_clk_enable; + + exynos_drm_crtc_from_pipe(drm_dev, pipe)->pipe_clk = &hdata->phy_clk; + encoder->possible_crtcs = 1 << pipe; DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);