From patchwork Wed Mar 23 13:26:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 8650081 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 19A769F38C for ; Wed, 23 Mar 2016 13:26:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F12D7203DB for ; Wed, 23 Mar 2016 13:26:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B6BC520397 for ; Wed, 23 Mar 2016 13:26:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A74606E85C; Wed, 23 Mar 2016 13:26:21 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id B92F66E865 for ; Wed, 23 Mar 2016 13:26:17 +0000 (UTC) Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4H00G2VUNS39A0@mailout2.w1.samsung.com> for dri-devel@lists.freedesktop.org; Wed, 23 Mar 2016 13:26:16 +0000 (GMT) X-AuditID: cbfec7f4-f796c6d000001486-ec-56f29978f9a1 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id C7.9E.05254.87992F65; Wed, 23 Mar 2016 13:26:16 +0000 (GMT) Received: from amdc1061.digital.local ([106.116.147.88]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4H0086MUNPPA00@eusync4.samsung.com>; Wed, 23 Mar 2016 13:26:16 +0000 (GMT) From: Andrzej Hajda To: Inki Dae Subject: [PATCH 6/6] drm/exynos: convert clock_enable crtc callback to pipeline clock Date: Wed, 23 Mar 2016 14:26:02 +0100 Message-id: <1458739562-32327-7-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1458739562-32327-1-git-send-email-a.hajda@samsung.com> References: <1458739562-32327-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgluLIzCtJLcpLzFFi42I5/e/4Nd2KmZ/CDF6ekrC4te4cq8XGGetZ La58fc9mMen+BBaLs01v2C1mnN/HZLH2yF12B3aP+93HmTz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4+W7nIJnOhXN17kbGI+pdjFyckgImEjcf9PFBGGLSVy4t54NxBYSWMoocaelsIuR C8huYpLYemYFM0iCTUBT4u/mm2BFIgLKEqv2tbODFDEL3GOS+HbhKVhCWCBc4kLHVXYQm0VA VaJ50Q2wZl4BZ4nGM69YILbJSZw8NpkVxOYUcJGYdqEHarOzxPrJi5knMPIuYGRYxSiaWppc UJyUnmuoV5yYW1yal66XnJ+7iRESPl92MC4+ZnWIUYCDUYmHV+LMxzAh1sSy4srcQ4wSHMxK IrySUz+FCfGmJFZWpRblxxeV5qQWH2KU5mBREuedu+t9iJBAemJJanZqakFqEUyWiYNTqoHR O01thdav64wpZYEr3IsdX1csWnym0LDfM6osKH+JyfnEDGsL2TjT6cln3pQdtJX/4XDs9Jyn OtEfuWNY9GoeRL1cE3F3Vndp4ey8s4LLj579MuPklFstzR4v37nq3W4L03Xssm9jMDv4lPm2 6wefGfa2y50Y496LpYluvt814fGENUXbQjYosRRnJBpqMRcVJwIA0lSssxsCAAA= Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , "open list:DRM DRIVERS FOR EXYNOS" , Andrzej Hajda , Kyungmin Park , Marek Szyprowski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP clock_enable callback is used only by FIMD->DP pipeline. Similar but more universal functionality provides pipeline clock. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_dp_core.c | 8 ++------ drivers/gpu/drm/exynos/exynos_drm_drv.h | 5 ----- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 27 +++++++++++++-------------- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c index cff8dc7..ebb96eb 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.c +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c @@ -1054,7 +1054,6 @@ static int exynos_dp_bridge_attach(struct drm_bridge *bridge) static void exynos_dp_bridge_enable(struct drm_bridge *bridge) { struct exynos_dp_device *dp = bridge->driver_private; - struct exynos_drm_crtc *crtc = dp_to_crtc(dp); if (dp->dpms_mode == DRM_MODE_DPMS_ON) return; @@ -1068,8 +1067,7 @@ static void exynos_dp_bridge_enable(struct drm_bridge *bridge) } } - if (crtc->ops->clock_enable) - crtc->ops->clock_enable(dp_to_crtc(dp), true); + exynos_drm_pipe_clk_enable(dp_to_crtc(dp), true); phy_power_on(dp->phy); exynos_dp_init_dp(dp); @@ -1082,7 +1080,6 @@ static void exynos_dp_bridge_enable(struct drm_bridge *bridge) static void exynos_dp_bridge_disable(struct drm_bridge *bridge) { struct exynos_dp_device *dp = bridge->driver_private; - struct exynos_drm_crtc *crtc = dp_to_crtc(dp); if (dp->dpms_mode != DRM_MODE_DPMS_ON) return; @@ -1098,8 +1095,7 @@ static void exynos_dp_bridge_disable(struct drm_bridge *bridge) flush_work(&dp->hotplug_work); phy_power_off(dp->phy); - if (crtc->ops->clock_enable) - crtc->ops->clock_enable(dp_to_crtc(dp), false); + exynos_drm_pipe_clk_enable(dp_to_crtc(dp), false); if (dp->panel) { if (drm_panel_unprepare(dp->panel)) diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 6ee0b20..1542910 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -129,10 +129,6 @@ struct exynos_drm_plane_config { * @disable_plane: disable hardware specific overlay. * @te_handler: trigger to transfer video image at the tearing effect * synchronization signal if there is a page flip request. - * @clock_enable: optional function enabling/disabling display domain clock, - * called from exynos-dp driver before powering up (with - * 'enable' argument as true) and after powering down (with - * 'enable' as false). */ struct exynos_drm_crtc; struct exynos_drm_crtc_ops { @@ -151,7 +147,6 @@ struct exynos_drm_crtc_ops { struct exynos_drm_plane *plane); void (*atomic_flush)(struct exynos_drm_crtc *crtc); void (*te_handler)(struct exynos_drm_crtc *crtc); - void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable); }; struct exynos_drm_clk { diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 51d484a..004bf57 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -102,6 +102,7 @@ struct fimd_driver_data { unsigned int has_vidoutcon:1; unsigned int has_vtsel:1; unsigned int has_mic_bypass:1; + unsigned int has_dp_clk:1; }; static struct fimd_driver_data s3c64xx_fimd_driver_data = { @@ -145,6 +146,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data = { .has_shadowcon = 1, .has_vidoutcon = 1, .has_vtsel = 1, + .has_dp_clk = 1, }; static struct fimd_driver_data exynos5420_fimd_driver_data = { @@ -157,6 +159,7 @@ static struct fimd_driver_data exynos5420_fimd_driver_data = { .has_vidoutcon = 1, .has_vtsel = 1, .has_mic_bypass = 1, + .has_dp_clk = 1, }; struct fimd_context { @@ -184,6 +187,7 @@ struct fimd_context { struct fimd_driver_data *driver_data; struct drm_encoder *encoder; + struct exynos_drm_clk dp_clk; }; static const struct of_device_id fimd_driver_dt_match[] = { @@ -878,21 +882,12 @@ static void fimd_te_handler(struct exynos_drm_crtc *crtc) drm_crtc_handle_vblank(&ctx->crtc->base); } -static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) +static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable) { - struct fimd_context *ctx = crtc->ctx; - u32 val; - - /* - * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE - * clock. On these SoCs the bootloader may enable it but any - * power domain off/on will reset it to disable state. - */ - if (ctx->driver_data != &exynos5_fimd_driver_data || - ctx->driver_data != &exynos5420_fimd_driver_data) - return; + struct fimd_context *ctx = container_of(clk, struct fimd_context, + dp_clk); + u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; - val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; writel(val, ctx->regs + DP_MIE_CLKCON); } @@ -908,7 +903,6 @@ static const struct exynos_drm_crtc_ops fimd_crtc_ops = { .disable_plane = fimd_disable_plane, .atomic_flush = fimd_atomic_flush, .te_handler = fimd_te_handler, - .clock_enable = fimd_dp_clock_enable, }; static irqreturn_t fimd_irq_handler(int irq, void *dev_id) @@ -987,6 +981,11 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) if (IS_ERR(ctx->crtc)) return PTR_ERR(ctx->crtc); + if (ctx->driver_data->has_dp_clk) { + ctx->dp_clk.enable = fimd_dp_clock_enable; + ctx->crtc->pipe_clk = &ctx->dp_clk; + } + if (ctx->encoder) exynos_dpi_bind(drm_dev, ctx->encoder);