@@ -4591,6 +4591,9 @@ static void intel_dp_get_dfp(struct intel_dp *intel_dp)
if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
+ } else if (!(intel_dp->dfp.type & DP_DS_PORT_TYPE_WIRELESS)) {
+ intel_dp->dfp.tmds_clk = DIV_ROUND_CLOSEST(dfp_info[1] * 25 * 1000, 10);
+ DRM_DEBUG_KMS("max TMDS clock is %d kHz\n", intel_dp->dfp.tmds_clk);
}
}
}
@@ -799,6 +799,7 @@ struct intel_dp_dfp {
int type;
bool detailed_cap_info;
int dot_clk; /* pixel rate for VGA dongles */
+ int tmds_clk;
};
struct intel_dp {
@@ -1170,13 +1170,14 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder)
static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
{
struct drm_device *dev = intel_hdmi_to_dev(hdmi);
+ int tmds_clock = hdmi_to_dig_port(hdmi)->dp.dfp.tmds_clk;
if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
- return 165000;
+ return (tmds_clock > 0 ? min(165000, tmds_clock) : 165000);
else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
- return 300000;
+ return (tmds_clock > 0 ? min(300000, tmds_clock) : 300000);
else
- return 225000;
+ return (tmds_clock > 0 ? min(225000, tmds_clock) : 225000);
}
static enum drm_mode_status
Read TMDS clock rate from DPCD for HDMI to filter out modes that might require higher TMDS clock rate than supported. Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++--- 3 files changed, 8 insertions(+), 3 deletions(-)