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Tue, 3 May 2016 11:05:41 -0400 From: Vitaly Prosyak To: Subject: [PATCH] drm/edid : cache edid range limits in drm connector Date: Tue, 3 May 2016 11:05:24 -0400 Message-ID: <1462287925-2668-1-git-send-email-vitaly.prosyak@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.22; IPV:CAL; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(428002)(199003)(189002)(6806005)(92566002)(50986999)(5008740100001)(86362001)(2351001)(229853001)(50226002)(33646002)(8936002)(450100001)(5003600100002)(47776003)(48376002)(77096005)(5003940100001)(19580405001)(19580395003)(110136002)(87936001)(105586002)(50466002)(189998001)(4326007)(36756003)(11100500001)(586003)(1220700001)(101416001)(53416004)(106466001); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR12MB0706; H:SATLEXCHOV02.amd.com; FPR:; SPF:None; MLV:sfv; A:1; MX:1; LANG:en; X-MS-Office365-Filtering-Correlation-Id: 2bfb7706-a3dc-47d9-0995-08d373646a65 X-Microsoft-Exchange-Diagnostics: 1; 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Ip=[165.204.84.22]; Helo=[SATLEXCHOV02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR12MB0706 Cc: Vitaly Prosyak X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Cache in drm connector the edid range limits properties: min/max vertical refresh rates and max pixel clock. It would be used when enter to drr mode. Signed-off-by: Vitaly Prosyak --- drivers/gpu/drm/drm_edid.c | 11 +++++++++++ include/drm/drm_crtc.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 04cb487..7e49962 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2190,6 +2190,17 @@ do_inferred_modes(struct detailed_timing *timing, void *c) timing); break; case 0x01: /* just the ranges, no formula */ + closure->connector->min_vfreq = range->min_vfreq; + closure->connector->max_vfreq = range->max_vfreq; + if (closure->edid->revision >= 4) { + if ((range->flags & 0x03) == 0x3) + closure->connector->min_vfreq += 255; + if (range->flags & 0x02) + closure->connector->max_vfreq += 255; + } + closure->connector->max_pixel_clock_khz = + range_pixel_clock(closure->edid, (u8 *)timing); + break; default: break; } diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index c5b4b81..85fc554 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1230,6 +1230,11 @@ struct drm_connector { uint8_t num_h_tile, num_v_tile; uint8_t tile_h_loc, tile_v_loc; uint16_t tile_h_size, tile_v_size; + + /*EDID range limits for drr*/ + int min_vfreq ; + int max_vfreq ; + int max_pixel_clock_khz; }; /**