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[1/3] drm/amdgpu/gfx8: fix CP jump table size

Message ID 1465567992-1353-1-git-send-email-alexander.deucher@amd.com (mailing list archive)
State New, archived
Headers show

Commit Message

Alex Deucher June 10, 2016, 2:13 p.m. UTC 
Align to the jump table offset. Fixes hangs on some
systems with GFX PG enabled.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Nicolai Hähnle June 13, 2016, 6:58 a.m. UTC | #1 
For the series:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

This patch is also:

Tested-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

On 10.06.2016 16:13, Alex Deucher wrote:
> Align to the jump table offset. Fixes hangs on some
> systems with GFX PG enabled.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 4e34877..42dc5fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1299,7 +1299,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
>
>   	if ((adev->asic_type == CHIP_CARRIZO) ||
>   	    (adev->asic_type == CHIP_STONEY)) {
> -		adev->gfx.rlc.cp_table_size = (96 * 5 * 4) + (64 * 1024); /* JT + GDS */
> +		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
>   		if (adev->gfx.rlc.cp_table_obj == NULL) {
>   			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
>   					     AMDGPU_GEM_DOMAIN_VRAM,
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4e34877..42dc5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1299,7 +1299,7 @@  static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
 
 	if ((adev->asic_type == CHIP_CARRIZO) ||
 	    (adev->asic_type == CHIP_STONEY)) {
-		adev->gfx.rlc.cp_table_size = (96 * 5 * 4) + (64 * 1024); /* JT + GDS */
+		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 		if (adev->gfx.rlc.cp_table_obj == NULL) {
 			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
 					     AMDGPU_GEM_DOMAIN_VRAM,