From patchwork Thu Jun 16 11:36:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9180621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BB1896075D for ; Thu, 16 Jun 2016 11:39:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4BA327BFF for ; Thu, 16 Jun 2016 11:39:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 99731282FF; Thu, 16 Jun 2016 11:39:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E23F27BFF for ; Thu, 16 Jun 2016 11:39:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E31666E270; Thu, 16 Jun 2016 11:38:52 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D6F18931E for ; Thu, 16 Jun 2016 11:38:20 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5768761420; Thu, 16 Jun 2016 11:38:20 +0000 (UTC) Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8879F614E0; Thu, 16 Jun 2016 11:38:17 +0000 (UTC) From: Archit Taneja To: robdclark@gmail.com Subject: [PATCH 18/22] dt-bindings: msm/mdp4: Create a separate binding doc for MDP4 Date: Thu, 16 Jun 2016 17:06:43 +0530 Message-Id: <1466077007-26792-19-git-send-email-architt@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1466077007-26792-1-git-send-email-architt@codeaurora.org> References: <1466077007-26792-1-git-send-email-architt@codeaurora.org> Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP MDP4 and MDP5 vary a bit in terms of device hierarchy and the properties they require. Rename the binding doc to mdp4.txt and remove MDP5 specific pieces. A separate document will be created for MDP5 Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja Acked-by: Rob Herring --- .../devicetree/bindings/display/msm/mdp.txt | 57 ---------------------- .../devicetree/bindings/display/msm/mdp4.txt | 54 ++++++++++++++++++++ 2 files changed, 54 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/mdp.txt create mode 100644 Documentation/devicetree/bindings/display/msm/mdp4.txt diff --git a/Documentation/devicetree/bindings/display/msm/mdp.txt b/Documentation/devicetree/bindings/display/msm/mdp.txt deleted file mode 100644 index ebfe016..0000000 --- a/Documentation/devicetree/bindings/display/msm/mdp.txt +++ /dev/null @@ -1,57 +0,0 @@ -Qualcomm adreno/snapdragon display controller - -Required properties: -- compatible: - * "qcom,mdp4" - mdp4 - * "qcom,mdp5" - mdp5 -- reg: Physical base address and length of the controller's registers. -- interrupts: The interrupt signal from the display controller. -- connectors: array of phandles for output device(s) -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - For MDP4: - * "core_clk" - * "iface_clk" - * "bus_clk" - * "lut_clk" - * "hdmi_clk" - * "tv_clk" - For MDP5: - * "bus_clk" - * "iface_clk" - * "core_clk" - * "lut_clk" (some MDP5 versions may not need this) - * "vsync_clk" - -Optional properties: -- gpus: phandle for gpu device -- clock-names: the following clocks are optional: - * "lut_clk" - -Example: - -/ { - ... - - mdp: qcom,mdp@5100000 { - compatible = "qcom,mdp4"; - reg = <0x05100000 0xf0000>; - interrupts = ; - connectors = <&hdmi>; - gpus = <&gpu>; - clock-names = - "core_clk", - "iface_clk", - "lut_clk", - "hdmi_clk", - "tv_clk"; - clocks = - <&mmcc MDP_CLK>, - <&mmcc MDP_AHB_CLK>, - <&mmcc MDP_AXI_CLK>, - <&mmcc MDP_LUT_CLK>, - <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.txt b/Documentation/devicetree/bindings/display/msm/mdp4.txt new file mode 100644 index 0000000..1de9b17 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdp4.txt @@ -0,0 +1,54 @@ +Qualcomm adreno/snapdragon MDP4 display controller + +Description: + +This is the bindings documentation for the MDP4 display controller found in +SoCs like MSM8960, APQ8064 and MSM8660. + +Required properties: +- compatible: + * "qcom,mdp4" - mdp4 +- reg: Physical base address and length of the controller's registers. +- interrupts: The interrupt signal from the display controller. +- connectors: array of phandles for output device(s) +- clocks: device clocks + See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required. + * "core_clk" + * "iface_clk" + * "bus_clk" + * "lut_clk" + * "hdmi_clk" + * "tv_clk" + +Optional properties: +- gpus: phandle for gpu device +- clock-names: the following clocks are optional: + * "lut_clk" + +Example: + +/ { + ... + + mdp: qcom,mdp@5100000 { + compatible = "qcom,mdp4"; + reg = <0x05100000 0xf0000>; + interrupts = ; + connectors = <&hdmi>; + gpus = <&gpu>; + clock-names = + "core_clk", + "iface_clk", + "lut_clk", + "hdmi_clk", + "tv_clk"; + clocks = + <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_AXI_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + }; +};